[PATCH net-next v3 0/2] net: pcs: rzn1-miic: Support configurable PHY_LINK polarity
From: Prabhakar <prabhakar.csengg@gmail.com>
Date: 2026-01-12 17:36:05
Also in:
linux-devicetree, linux-renesas-soc, lkml
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi all, This series adds support for configuring the active level of MIIC PHY_LINK status signals on Renesas RZ/N1 and RZ/T2H/N2H platforms. The MIIC block provides dedicated hardware PHY_LINK signals that indicate EtherPHY link-up and link-down status independently of whether the MAC (GMAC) or Ethernet switch (ETHSW) is used. While GMAC-based systems typically obtain link state via MDIO and handle it in software, the ETHSW relies on these PHY_LINK pins for both CPU-assisted operation and switch-only forwarding paths that do not involve the host processor. These hardware PHY_LINK signals are particularly important for use cases requiring fast reaction to link-down events, such as redundancy protocols including Device Level Ring (DLR). In such scenarios, relying solely on software-based link detection introduces latency that can negatively impact recovery time. The ETHSW therefore exposes PHY_LINK signals to enable immediate hardware-level detection of cable or port failures. Some systems require the PHY_LINK signal polarity to be configured as active low rather than the default active high. This series introduces a new DT property to describe the required polarity and adds corresponding driver support to program the MIIC PHY_LINK register accordingly. The configuration is accumulated during DT parsing and applied once hardware initialization is complete, taking into account SoC-specific differences between RZ/N1 and RZ/T2H/N2H. Thanks for your review. v2->v3: - Updated commit message for patches 1 and 2 to improve clarity - Renemaed DT property from renesas,miic-phylink-active-low to renesas,miic-phy-link-active-low. - Updated references of PHYLINK to PHY_LINK and phylink to phy_link in code to avoid confusion with the Linux phylink subsystem. - Simplified the PHY_LINK configuration parsing logic in the driver as suggested. v1->v2: - Updated commit message to elaborate the necessity of PHY link signals Best regards, Prabhakar Lad Prabhakar (2): dt-bindings: net: pcs: renesas,rzn1-miic: Add phy_link property net: pcs: rzn1-miic: Add PHY_LINK active-level configuration support .../bindings/net/pcs/renesas,rzn1-miic.yaml | 7 ++ drivers/net/pcs/pcs-rzn1-miic.c | 105 +++++++++++++++++- 2 files changed, 109 insertions(+), 3 deletions(-) -- 2.52.0