RE: [Intel-wired-lan] [PATCH RFC net-next 13/13] ice: dpll: Support E825-C SyncE and dynamic pin discovery
From: Loktionov, Aleksandr <hidden>
Date: 2025-12-12 10:20:56
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-----Original Message----- From: Intel-wired-lan <redacted> On Behalf Of Ivan Vecera Sent: Thursday, December 11, 2025 8:48 PM To: netdev@vger.kernel.org; Andrew Lunn <andrew+netdev@lunn.ch>; David S. Miller [off-list ref]; Eric Dumazet [off-list ref]; Jakub Kicinski [off-list ref]; Paolo Abeni [off-list ref]; Rob Herring [off-list ref]; Krzysztof Kozlowski [off-list ref]; Conor Dooley [off-list ref]; Vadim Fedorenko [off-list ref]; Kubalewski, Arkadiusz [off-list ref]; Nitka, Grzegorz [off-list ref]; Jiri Pirko [off-list ref]; Oros, Petr [off-list ref]; Schmidt, Michal [off-list ref]; Prathosh Satish [off-list ref]; Nguyen, Anthony L [off-list ref]; Kitszel, Przemyslaw [off-list ref]; Saeed Mahameed [off-list ref]; Leon Romanovsky [off-list ref]; Tariq Toukan [off-list ref]; Mark Bloch [off-list ref]; Richard Cochran [off-list ref]; Jonathan Lemon [off-list ref]; Simon Horman [off-list ref]; Lobakin, Aleksander [off-list ref]; Willem de Bruijn [off-list ref]; Stefan Wahren [off-list ref]; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; intel- wired-lan@lists.osuosl.org; linux-rdma@vger.kernel.org Subject: [Intel-wired-lan] [PATCH RFC net-next 13/13] ice: dpll: Support E825-C SyncE and dynamic pin discovery From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Add DPLL support for the Intel E825-C Ethernet controller. Unlike previous generations (E810), the E825-C connects to the platform's DPLL subsystem via MUX pins defined in the system firmware (Device Tree/ACPI). Implement the following mechanisms to support this architecture: 1. Dynamic Pin Discovery: Use the fwnode_dpll_pin_find() helper to locate the parent MUX pins defined in the firmware. 2. Asynchronous Registration: Since the platform DPLL driver may probe independently of the network driver, utilize the DPLL notifier chain (register_dpll_notifier). The driver listens for DPLL_PIN_CREATED events to detect when the parent MUX pins become available, then registers its own Recovered Clock (RCLK) and PTP (1588) pins as children of those parents. 3. Hardware Configuration: Implement the specific register access logic for E825-C CGU (Clock Generation Unit) registers (R10, R11). This includes configuring the bypass MUXes and clock dividers required to drive SyncE and PTP signals. 4. Split Initialization: Refactor `ice_dpll_init()` to separate the static initialization path of E810 from the dynamic, firmware- driven path required for E825-C. Co-developed-by: Ivan Vecera <ivecera@redhat.com> Co-developed-by: Grzegorz Nitka <redacted> Signed-off-by: Ivan Vecera <ivecera@redhat.com> Signed-off-by: Grzegorz Nitka <redacted> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> --- drivers/net/ethernet/intel/ice/ice_dpll.c | 964 ++++++++++++++++++-- drivers/net/ethernet/intel/ice/ice_dpll.h | 29 + drivers/net/ethernet/intel/ice/ice_lib.c | 3 + drivers/net/ethernet/intel/ice/ice_ptp.c | 29 + drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 9 +- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 1 + drivers/net/ethernet/intel/ice/ice_tspll.c | 223 +++++ drivers/net/ethernet/intel/ice/ice_tspll.h | 14 +- drivers/net/ethernet/intel/ice/ice_type.h | 6 + 9 files changed, 1188 insertions(+), 90 deletions(-)diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c
...
+static int
+ice_dpll_pin_get_parent_num(struct ice_dpll_pin *pin,
+ const struct dpll_pin *parent)
+{
+ int i;
+
+ for (i = 0; pin->num_parents; i++)
+ if (pin->pf->dplls.inputs[pin->parent_idx[i]].pin ==
parent)Oh, no! we don't need a 2nd Infinite Loop in Cupertino! ...
-- 2.51.2