[PATCH net-next V2 2/3] net/mlx5e: Add 1600Gbps link modes
From: Tariq Toukan <tariqt@nvidia.com>
Date: 2025-11-19 20:49:08
Also in:
linux-rdma, lkml
Subsystem:
mellanox ethernet driver (mlx5e), mellanox mlx5 core vpi driver, networking drivers, the rest · Maintainers:
Saeed Mahameed, Tariq Toukan, Mark Bloch, Leon Romanovsky, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
From: Yael Chemla <redacted> Introduce support for a 1600Gbps link mode, utilizing 8 lanes at 200Gbps per lane. Signed-off-by: Yael Chemla <redacted> Reviewed-by: Shahar Shitrit <redacted> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> --- drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | 5 +++++ drivers/net/ethernet/mellanox/mlx5/core/port.c | 1 + 2 files changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
index 727d7a833110..fe67c73849f9 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c@@ -261,6 +261,11 @@ void mlx5e_build_ptys2ethtool_map(void) ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT, ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT, ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT); + MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1600TAUI_8_1600TBASE_CR8_KR8, ext, + ETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT, + ETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT, + ETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT, + ETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT); } static void mlx5e_ethtool_get_speed_arr(bool ext,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c
index e4b1dfafb41f..85a9e534f442 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/port.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c@@ -1108,6 +1108,7 @@ mlx5e_ext_link_info[MLX5E_EXT_LINK_MODES_NUMBER] = { [MLX5E_200GAUI_1_200GBASE_CR1_KR1] = {.speed = 200000, .lanes = 1}, [MLX5E_400GAUI_2_400GBASE_CR2_KR2] = {.speed = 400000, .lanes = 2}, [MLX5E_800GAUI_4_800GBASE_CR4_KR4] = {.speed = 800000, .lanes = 4}, + [MLX5E_1600TAUI_8_1600TBASE_CR8_KR8] = {.speed = 1600000, .lanes = 8}, }; int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,
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2.31.1