Thread (7 messages) 7 messages, 5 authors, 2025-11-05
STALE206d

[PATCH v2 1/1] dt-bindings: net: ethernet-phy: clarify when compatible must specify PHY ID

From: Buday Csaba <hidden>
Date: 2025-11-03 08:13:59
Also in: linux-devicetree, lkml
Subsystem: ethernet phy library, networking drivers, open firmware and flattened device tree bindings, the rest · Maintainers: Andrew Lunn, Heiner Kallweit, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds

Change PHY ID description in ethernet-phy.yaml to clarify that a
PHY ID is required (may -> must) when the PHY requires special
initialization sequence.

Link: https://lore.kernel.org/netdev/20251026212026.GA2959311-robh@kernel.org/ (local)
Link: https://lore.kernel.org/netdev/aQIZvDt5gooZSTcp@debianbuilder/ (local)

Signed-off-by: Buday Csaba <redacted>
---
V1 -> V2: Changed wording on maintainer request.
---
 .../devicetree/bindings/net/ethernet-phy.yaml          | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
index 2ec2d9fda..bb4c49fc5 100644
--- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
@@ -35,9 +35,13 @@ properties:
         description: PHYs that implement IEEE802.3 clause 45
       - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
         description:
-          If the PHY reports an incorrect ID (or none at all) then the
-          compatible list may contain an entry with the correct PHY ID
-          in the above form.
+          PHYs contain identification registers. These will be read to
+          identify the PHY. If the PHY reports an incorrect ID, or the
+          PHY requires a specific initialization sequence (like a
+          particular order of clocks, resets, power supplies), in
+          order to be able to read the ID registers, then the
+          compatible list must contain an entry with the correct PHY
+          ID in the above form.
           The first group of digits is the 16 bit Phy Identifier 1
           register, this is the chip vendor OUI bits 3:18. The
           second group of digits is the Phy Identifier 2 register,
base-commit: 0d0eb186421d0886ac466008235f6d9eedaf918e
-- 
2.39.5

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