On 10/30/25 1:17 PM, Russell King (Oracle) wrote:
Konrad, Ayaan,
Can you shed any light on the manipulation of the RGMII_IO_MACRO_CONFIG
and RGMII_IO_MACRO_CONFIG2 registers in ethqos_configure_sgmii()?
Specifically:
- why would RGMII_CONFIG2_RGMII_CLK_SEL_CFG be set for 2.5G and 1G
speeds, but never be cleared for any other speed?
BIT(16) - "enable to transmit delayed clock in RGMII 100/10 ID Mode"
- why is RGMII_CONFIG_SGMII_CLK_DVDR set to SGMII_10M_RX_CLK_DVDR
for 10M, but never set to any other value for other speeds?
[18:10] - In short, it configures a divider. The expected value is 0x13
for 10 Mbps / RMII mode
which seems to have been problematic given:
https://lore.kernel.org/all/20231212092208.22393-1-quic_snehshah@quicinc.com/ (local)
But it didn't say what hardware had this issue.. whether it concerns a
specific SoC or all of them..
A programming guide mentions the new 0x31 value for 10 Mbps in a
SoC-common paragraph so I suppose it's indeed better-er.. Perhaps issues
could arise if you switch back to a faster mode?
To me, this code looks very suspicious.
If you have time, please test with a connection capable of 1000BASE-T,
100BASE-TX and 10BASE-T, modifying the advertisement to make it
negotiate each of these, and checking that packet transfer is still
possible.
No HW with an ethernet port at hand, sorry
Konrad