Hi Irving-ch,

On Fri, Sep 12, 2025 at 08:04:52PM +0800, irving.ch.lin wrote:

From: Irving-ch Lin <redacted>

Introduce a new clock (clk) driver port for the MediaTek
MT8189 SoC. The driver is newly implemented based on the hardware
layout and register settings of the MT8189 chip, enabling correct clk
management and operation for various modules.

With clock topology, we need to register clock sequence below:
apmixedsys(pll) -> topckgen(div/mux) -> others(cgs)

Signed-off-by: Irving-ch Lin <redacted>
---
drivers/clk/mediatek/Kconfig                 |  146 +++
drivers/clk/mediatek/Makefile                |   14 +
drivers/clk/mediatek/clk-mt8189-apmixedsys.c |  135 +++
drivers/clk/mediatek/clk-mt8189-bus.c        |  289 +++++
drivers/clk/mediatek/clk-mt8189-cam.c        |  131 +++
drivers/clk/mediatek/clk-mt8189-dbgao.c      |  115 ++
drivers/clk/mediatek/clk-mt8189-dvfsrc.c     |   61 +
drivers/clk/mediatek/clk-mt8189-iic.c        |  149 +++
drivers/clk/mediatek/clk-mt8189-img.c        |  122 ++
drivers/clk/mediatek/clk-mt8189-mdpsys.c     |  100 ++
drivers/clk/mediatek/clk-mt8189-mfg.c        |   56 +
drivers/clk/mediatek/clk-mt8189-mmsys.c      |  233 ++++
drivers/clk/mediatek/clk-mt8189-scp.c        |   92 ++
drivers/clk/mediatek/clk-mt8189-topckgen.c   | 1057 ++++++++++++++++++
drivers/clk/mediatek/clk-mt8189-ufs.c        |  106 ++
drivers/clk/mediatek/clk-mt8189-vcodec.c     |  119 ++
drivers/clk/mediatek/clk-mt8189-vlpcfg.c     |  145 +++
drivers/clk/mediatek/clk-mt8189-vlpckgen.c   |  280 +++++
drivers/clk/mediatek/clk-mux.c               |    4 +
19 files changed, 3354 insertions(+)

This is too much changes in a single patch. Prefer to separate
into small patches in next version, otherwise it is hard to review.

Regards
Peng