Re: [PATCH v4 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: 2025-08-07 06:58:13
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-mediatek, lkml
On Tue, Aug 05, 2025 at 03:54:29PM +0200, Laura Nao wrote:
Introduce binding documentation for system clocks, functional clocks, and PEXTP0/1 and UFS reset controllers on MediaTek MT8196. This binding also includes a handle to the hardware voter, a fixed-function MCU designed to aggregate votes from the application processor and other remote processors to manage clocks and power domains. The HWV on MT8196/MT6991 is incomplete and requires software to manually enable power supplies, parent clocks, and FENC, as well as write to both the HWV MMIO and the controller registers. Because of these constraints, the HWV cannot be modeled using generic clock, power domain, or interconnect APIs. Instead, a custom phandle is exceptionally used to provide direct, syscon-like register access to drivers. Reviewed-by: Nícolas F. R. A. Prado <redacted> Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Laura Nao <redacted> ---
Reviewed-by: Krzysztof Kozlowski <redacted> Best regards, Krzysztof