-----Original Message-----
From: Geert Uytterhoeven <geert@linux-m68k.org>
Sent: 25 June 2025 16:17
Subject: Re: [PATCH v3 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces

Hi John,

On Mon, 23 Jun 2025 at 10:04, John Madieu [off-list ref] wrote:

quoted

Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E
SMARC EVK

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

quoted

v3:
Updates mdio separately, based on phandles instead of node
redefinition

Thanks for the update!

quoted

--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi

quoted

 &pinctrl {
+       eth0_pins: eth0 {
+               pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
+                        <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
+                        <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
+                        <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
+                        <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
+                        <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
+                        <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
+                        <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
+                        <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
+                        <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
+                        <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
+                        <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
+                        <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
+                        <RZG3E_PORT_PINMUX(B, 1, 1)>, /* TXC */
+                        <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
+       };
+
+       eth1_pins: eth1 {
+               pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
+                        <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
+                        <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
+                        <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
+                        <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
+                        <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
+                        <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
+                        <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
+                        <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
+                        <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
+                        <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
+                        <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
+                        <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
+                        <RZG3E_PORT_PINMUX(E, 1, 1)>, /* TXC */
+                        <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
+       };
+
        i2c2_pins: i2c {
                pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
                         <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */

Based on the feedback from Prabhakar on v2, I understand this needs to configure output-enable for the
ET0_TXC_TXCLK and ET1_TXC_TXCLK pins, and to add support for that in the pin control driver first?

[1] https://lore.kernel.org/all/CA+V-a8uizu5MCur_=g5vJyWbWSTSP2J6FkQ89JB8ges7GWdsjg@mail.gmail.com/ (local)

Maybe this could be the reason for RZ/V2H sees clock monitor issue during unbind/bind and RZ/G3E don't see it when
using DEF_MOD macro. Maybe after this change, It may trigger the clock monitor issue on RZ/G3E as well
forcing to use DEF_MOD_EXTERNAL??

Cheers,
Biju