On Friday, 30 May 2025 09:46:19 CEST Russell King (Oracle) wrote:

On Fri, May 30, 2025 at 09:28:11AM +0200, Romain Gantois wrote:

quoted

On Thursday, 29 May 2025 15:23:22 CEST Russell King (Oracle) wrote:

quoted

On Wed, May 28, 2025 at 09:35:35AM +0200, Romain Gantois wrote:

quoted

quoted

In that regard, you can consider 1000BaseX as a MII mode (we do have
PHY_INTERFACE_MODE_1000BASEX).

Ugh, the "1000BaseX" terminology never ceases to confuse me, but yes
you're
right.

1000BASE-X is exactly what is described in IEEE 802.3. It's a PHY
interface mode because PHYs that use SerDes can connect to the host
using SGMII or 1000BASE-X over the serial link.

1000BASE-X's purpose in IEEE 802.3 is as a protocol for use over
fibre links, as the basis for 1000BASE-SX, 1000BASE-LX, 1000BASE-EX
etc where the S, L, E etc are all to do with the properties of the
medium that the electrical 1000BASE-X is sent over. It even includes
1000BASE-CX which is over copper cable.

Ah makes sense, thanks for the explanation. I guess my mistake was
assuming
that MAC/PHY interface modes were necessarily strictly at the
reconciliation sublayer level, and didn't include PCS/PMA functions.

When a serdes protocol such as SGMII, 1000BASE-X, or 10GBASE-R is being
used with a PHY, the IEEE 802.3 setup isn't followed exactly - in
effect there are more layers.

On the SoC:

	MAC
	Reconciliation (RS)
	PCS
	SerDes (part of the PMA layer)

On the PHY side of the SerDes host-to-phy link:

	SerDes
	PCS (which may or may not be exposed in the PHY register set,
	     and is normally managed by the PHY itself)
	(maybe other layers, could include MACs	back-to-back)
	PCS
	PMA
	PMD

Hope that helps explain what's going on a little more.

Definitely helps a lot, thanks.

-- 
Romain Gantois, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com