On Mon, Mar 31, 2025 at 03:09:00PM -0400, Da Xue wrote:

On Mon, Mar 31, 2025 at 9:55 AM Russell King (Oracle)
[off-list ref] wrote:

quoted

On Mon, Mar 31, 2025 at 03:43:26PM +0200, Andrew Lunn wrote:

quoted

On Mon, Mar 31, 2025 at 07:44:20AM +0000, Christian Hewitt wrote:

quoted

From: Da Xue <redacted>

This bit is necessary to enable packets on the interface. Without this
bit set, ethernet behaves as if it is working, but no activity occurs.

The vendor SDK sets this bit along with the PHY_ID bits. U-boot also
sets this bit, but if u-boot is not compiled with networking support
the interface will not work.

Fixes: 9a24e1ff4326 ("net: mdio: add amlogic gxl mdio mux support");
Signed-off-by: Da Xue <redacted>
Signed-off-by: Christian Hewitt <redacted>
---
Resending on behalf of Da Xue who has email sending issues.
Changes since v1 [0]:
- Remove blank line between Fixes and SoB tags
- Submit without mail server mangling the patch
- Minor tweaks to subject line and commit message
- CC to stable@vger.kernel.org

[0] https://patchwork.kernel.org/project/linux-amlogic/patch/CACqvRUbx-KsrMwCHYQS6eGXBohynD8Q1CQx=8=9VhqZi13BCQQ@mail.gmail.com/

 drivers/net/mdio/mdio-mux-meson-gxl.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mdio/mdio-mux-meson-gxl.c b/drivers/net/mdio/mdio-mux-meson-gxl.c
index 00c66240136b..fc5883387718 100644
--- a/drivers/net/mdio/mdio-mux-meson-gxl.c
+++ b/drivers/net/mdio/mdio-mux-meson-gxl.c

@@ -17,6 +17,7 @@
 #define  REG2_LEDACT               GENMASK(23, 22)
 #define  REG2_LEDLINK              GENMASK(25, 24)
 #define  REG2_DIV4SEL              BIT(27)
+#define  REG2_RESERVED_28  BIT(28)

It must have some meaning, it cannot be reserved. So lets try to find
a better name.

Indeed, that was my thoughts as well, but Andrew got his reply in
before I got around to replying!

The datasheets don't have much in the way of information about this
register bit. The Amlogic GXL datasheet is notoriously inaccurate.

ETH_REG2 0XC8834558
29:28 R 0x1 reserved

It claims the bit is read only while the BSP hard codes the setting of
this register. I am open to any name for this register bit.
This is the only thing holding up distro netbooting for these very
popular chip family.

Which interface mode do we think this affects?

As a suggestion, maybe call it:

REG2_<interfacemode>_EN

and possibly add a comment "This bit is documented as reserved, but
needs to be set so that <interfacemode> can pass traffic. This is
an unofficial name."

-- 
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