[PATCH v10 5/6] arm64: dts: qcom: ipq9574: Add nsscc node
From: Manikanta Mylavarapu <hidden>
Date: 2025-02-21 10:15:58
Also in:
linux-arm-kernel, linux-arm-msm, linux-clk, linux-devicetree, lkml
Subsystem:
arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
From: Devi Priya <redacted> Add a node for the nss clock controller found on ipq9574 based devices. Signed-off-by: Devi Priya <redacted> Signed-off-by: Manikanta Mylavarapu <redacted> --- Changes in V10: - Added clock-names. - Dropped #power-domain-cells from nsscc node, because nsscc doesn't provide any power domains. arch/arm64/boot/dts/qcom/ipq9574.dtsi | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 942290028972..bbb5bd7f8618 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi@@ -1193,6 +1193,35 @@ pcie0: pci@28000000 { status = "disabled"; }; + nsscc: clock-controller@39b00000 { + compatible = "qcom,ipq9574-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&xo_board_clk>, + <&cmn_pll NSS_1200MHZ_CLK>, + <&cmn_pll PPE_353MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_NSSCC_CLK>; + clock-names = "xo", + "nss_1200", + "ppe_353", + "gpll0_out", + "uniphy0_rx", + "uniphy0_tx", + "uniphy1_rx", + "uniphy1_tx", + "uniphy2_rx", + "uniphy2_tx", + "nsscc"; + #clock-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; }; thermal-zones {
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2.34.1