On 2/6/25 17:41, Kyle Hendry wrote:

On 2025-02-06 12:17, Andrew Lunn wrote:

quoted

On Thu, Feb 06, 2025 at 10:15:50AM -0800, Florian Fainelli wrote:

quoted

Hi Kyle,

On 2/5/25 20:30, Kyle Hendry wrote:

quoted

Some BCM63268 bootloaders do not enable the internal PHYs by default.
This patch series adds functionality for the switch driver to
configure the gigabit ethernet PHY.

Signed-off-by: Kyle Hendry <redacted>

So the register address you are manipulating logically belongs in the 
GPIO
block (GPIO_GPHY_CTRL) which has become quite a bit of a sundry here. I
don't have a strong objection about the approach picked up here but 
we will
need a Device Tree binding update describing the second (and optional)
register range.

Despite this being internal, is this actually a GPIO? Should it be
modelled as a GPIO line connected to a reset input on the PHY? It
would then nicely fit in the existing phylib handling of a PHY with a
GPIO reset line?

    Andrew

The main reason I took this approach is because a SF2 register has
similar bits and I wanted to be consistent with that driver. If it
makes more sense to treat these bits as GPIOs/clocks/resets then it
would make the implementation simpler.

I don't think there is a need to go that far, and I don't think any of 
those abstractions work really well in the sense that they are neither 
clocks, nor resets, nor GPIOs, they are just enable bits for the power 
gating logic of the PHY, power domains would be the closest to what this 
is, but this is a very heavy handed approach with little benefit IMHO.

What we do need is document this register in the binding however.
-- 
Florian