[PATCH 1/4] arm64: dts: agilex5: add gpio0
From: Steffen Trumtrar <hidden>
Date: 2024-10-30 12:10:22
Also in:
linux-clk, linux-devicetree, lkml
Subsystem:
arm/socfpga architecture, the rest · Maintainers:
Dinh Nguyen, Linus Torvalds
gpio0 is the same as gpio1 with a different base address. Signed-off-by: Steffen Trumtrar <redacted> --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 1162978329c1637aa0fd9a4adef16a9ae5017ac3..57c28e284cccdb99ede6cea2bc0e8dd8aaf47fe9 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi@@ -222,6 +222,26 @@ i3c1: i3c@10da1000 { status = "disabled"; }; + gpio0: gpio@10c03200 { + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03200 0x100>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + gpio1: gpio@10c03300 { compatible = "snps,dw-apb-gpio"; reg = <0x10c03300 0x100>;
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2.46.0