On Thu, Aug 29, 2024 at 01:21:20PM +0300, Dmitry Baryshkov wrote:

On Thu, Aug 29, 2024 at 01:58:29PM GMT, Varadarajan Narayanan wrote:

quoted

From: Kathiravan Thirumoorthy <redacted>

Describe the NSS clock controller node and it's relevant external
clocks.

Who generates these clocks? 300 MHz crystal?

These two clocks are from the output clocks of CMN PLL.
IPQ5332 CMN PLL patches similar to [1] are in the pipeline
and should get posted soon.

1: https://lore.kernel.org/all/20241015-qcom_ipq_cmnpll-v4-0-27817fbe3505@quicinc.com/ (local)

Thanks
Varada

quoted

Signed-off-by: Kathiravan Thirumoorthy <redacted>
Signed-off-by: Varadarajan Narayanan <redacted>
---
v5: Remove #power-domain-cells
    Add #interconnect-cells
---
 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 +++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 71328b223531..1cc614de845c 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi

@@ -16,6 +16,18 @@ / {
 	#size-cells = <2>;

 	clocks {
+		cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <200000000>;
+			#clock-cells = <0>;
+		};
+
+		cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <300000000>;
+			#clock-cells = <0>;
+		};
+
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;

@@ -479,6 +491,22 @@ frame@b128000 {
 				status = "disabled";
 			};
 		};
+
+		nsscc: clock-controller@39b00000 {
+			compatible = "qcom,ipq5332-nsscc";
+			reg = <0x39b00000 0x80000>;
+			clocks = <&cmn_pll_nss_200m_clk>,
+				 <&cmn_pll_nss_300m_clk>,
+				 <&gcc GPLL0_OUT_AUX>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <&xo_board>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#interconnect-cells = <1>;
+		};
 	};

 	timer {
--

2.34.1

--
With best wishes
Dmitry