[PATCH v3 16/16] net: stmmac: dwmac-s32: Read PTP clock rate when ready
From: Jan Petrous via B4 Relay <devnull+jan.petrous.oss.nxp.com@kernel.org>
Date: 2024-10-13 21:27:59
Also in:
b4-sent, imx, linux-arm-kernel, linux-arm-msm, linux-devicetree, lkml
Subsystem:
arm/nxp s32g/s32r dwmac ethernet driver, networking drivers, stmmac ethernet driver, the rest · Maintainers:
Jan Petrous, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Maxime Chevallier, Linus Torvalds
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> The PTP clock is read by stmmac_platform during DT parse. On S32G/R the clock is not ready and returns 0. Postpone reading of the clock on PTP init. Co-developed-by: Andrei Botila <redacted> Signed-off-by: Andrei Botila <redacted> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> --- drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
index aedd6bf80684..3daf282d8da7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c@@ -140,6 +140,18 @@ static void s32_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode) dev_err(gmac->dev, "Can't set tx clock\n"); } +static void s32_dwmac_ptp_clk_freq_config(struct stmmac_priv *priv) +{ + struct plat_stmmacenet_data *plat = priv->plat; + + if (!plat->clk_ptp_ref) + return; + + plat->clk_ptp_rate = clk_get_rate(plat->clk_ptp_ref); + + netdev_dbg(priv->dev, "PTP rate %lu\n", plat->clk_ptp_rate); +} + static int s32_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat;
@@ -195,6 +207,7 @@ static int s32_dwmac_probe(struct platform_device *pdev) plat->init = s32_gmac_init; plat->exit = s32_gmac_exit; plat->fix_mac_speed = s32_fix_mac_speed; + plat->ptp_clk_freq_config = s32_dwmac_ptp_clk_freq_config; plat->bsp_priv = gmac;
--
2.46.0