Re: [EXTERNAL] Re: [PATCH net-next v2 1/2] dt-bindings: net: Add documentation for Half duplex support.

On 12/09/23 20:46, Andrew Lunn wrote:

quoted

Sure Rob, I will change the description to below.

    description:
      Indicates that the PHY output pin (COL) is routed to ICSSG GPIO

The PHY has multiple output pins, so i would not put COL in brackets,
but make it explicit which pin you are referring to.

Sure, I will remove the brackets and make it explicit.

quoted

      pin (PRGx_PRU0/1_GPIO10) as input and ICSSG MII port is capable
      of half duplex operations.

"input and so the ICSSG MII port is"

I think "input so that the ICSSG MII port is" will be better.

The description would look something like below,

  description:
    Indicates that the PHY output pin COL is routed to ICSSG GPIO pin
    (PRGx_PRU0/1_GPIO10) as input so that the ICSSG MII port is
    capable of half duplex operations.

I will post the next version with this change.

       Andrew

-- 
Thanks and Regards,
Danish