Re: [RFC net-next v1 3/5] net: phy: nxp-c45-tja11xx add MACsec support

On 11.08.2023 20:10, Andrew Lunn wrote:

quoted

+#define VEND1_MACSEC_BASE		0x9000
+
+#define MACSEC_CFG			0x0000
+#define MACSEC_CFG_BYPASS		BIT(1)
+#define MACSEC_CFG_S0I			BIT(0)
+
+#define MACSEC_TPNET			0x0044

quoted

+static int nxp_c45_macsec_write(struct phy_device *phydev, u16 reg, u32 val)
+{
+	reg = reg / 2;

That is a bit odd. How does the data sheet describe these
registers. e.g. MACSEC_TPNET. Does it say 0x9022 and 0x9023?  It seems
it would be easy to mix this up and end up accessing 0x9011 and
0x9012.

	   Andrew

According to the MACsec IP user manual, the registers are 32 bits wide and the addresses are 4 byte aligned. The PHY translates two writes in two consecutive registers in one write in the MACsec IP.

I agree. It's too easy to write the wrong address here. I should check the address alignment.

-- 
Radu P.