-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: Monday, 7 August, 2023 3:35 AM
To: Rabara, Niravkumar L <redacted>
Cc: Ng, Adrian Ho Yin <redacted>; andrew@lunn.ch;
conor+dt@kernel.org; devicetree@vger.kernel.org; dinguyen@kernel.org;
krzysztof.kozlowski+dt@linaro.org; linux-clk@vger.kernel.org; linux-
kernel@vger.kernel.org; Turquette, Mike [off-list ref];
netdev@vger.kernel.org; p.zabel@pengutronix.de;
richardcochran@gmail.com; robh+dt@kernel.org; sboyd@kernel.org;
wen.ping.teh@intel.com
Subject: Re: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock
manager

On 01/08/2023 03:02, niravkumar.l.rabara@intel.com wrote:

quoted

From: Niravkumar L Rabara <redacted>

Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.

Signed-off-by: Teh Wen Ping <redacted>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Niravkumar L Rabara <redacted>
---

Do not attach (thread) your patchsets to some other threads (unrelated or
older versions). This buries them deep in the mailbox and might interfere
with applying entire sets.

Best regards,
Krzysztof

Sorry it was a mistake.
Will be careful now onwards.

Thanks,
Nirav