Hi Richard,

On 7/27/23 15:36, Richard Cochran wrote:

On Thu, Jul 27, 2023 at 09:20:10AM +0200, Johannes Zink wrote:

quoted

Hi Richard,

On 7/26/23 22:57, Richard Cochran wrote:

quoted

On Mon, Jul 24, 2023 at 12:01:31PM +0200, Johannes Zink wrote:

Earlier versions of the IP core return zero from these...

quoted

+#define	PTP_TS_INGR_LAT	0x68	/* MAC internal Ingress Latency */
+#define	PTP_TS_EGR_LAT	0x6c	/* MAC internal Egress Latency */

good catch. Gonna send a v3 with a check to and set the values for dwmac v5 only.

AFAICT there is no feature bit that indicates the presence or absence
of these two registers.

Are you sure that *all* v5 IP cores have these?

I am not sure.

I cannot tell for sure either, since I have datasheets for the i.MX8MP only. 
Maybe Kurt has some insights here, as he has additional hardware available for 
testing?

Nevertheless, I am going to add a guard to only use the correction codepath on 
i.MX8MP in v3 for the time being, we can add other hardware later trivially if 
they support doing this.

Best regards
Johannes

Thanks,
Richard

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