[PATCH net-next v2 8/9] ptp: idt82p33: Add .getmaxphase ptp_clock_info callback
From: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Date: 2023-05-23 20:56:31
Subsystem:
networking drivers, ptp hardware clock support, the rest · Maintainers:
Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Richard Cochran, Linus Torvalds
Advertise the maximum offset the .adjphase callback is capable of supporting in nanoseconds for IDT devices. This change refactors the negation of the offset stored in the register to be after the boundary check of the offset value rather than before. Boundary checking is done based on the intended value rather than its device-specific representation. Cc: Richard Cochran <richardcochran@gmail.com> Cc: Min Li <redacted> Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com> --- drivers/ptp/ptp_idt82p33.c | 18 +++++++++--------- drivers/ptp/ptp_idt82p33.h | 4 ++-- 2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c
index afc76c22271a..057190b9cd3d 100644
--- a/drivers/ptp/ptp_idt82p33.c
+++ b/drivers/ptp/ptp_idt82p33.c@@ -978,24 +978,23 @@ static int idt82p33_enable(struct ptp_clock_info *ptp, return err; } +static s32 idt82p33_getmaxphase(__always_unused struct ptp_clock_info *ptp) +{ + return WRITE_PHASE_OFFSET_LIMIT; +} + static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns) { struct idt82p33_channel *channel = container_of(ptp, struct idt82p33_channel, caps); struct idt82p33 *idt82p33 = channel->idt82p33; - s64 offset_regval, offset_fs; + s64 offset_regval; u8 val[4] = {0}; int err; - offset_fs = (s64)(-offset_ns) * 1000000; - - if (offset_fs > WRITE_PHASE_OFFSET_LIMIT) - offset_fs = WRITE_PHASE_OFFSET_LIMIT; - else if (offset_fs < -WRITE_PHASE_OFFSET_LIMIT) - offset_fs = -WRITE_PHASE_OFFSET_LIMIT; - /* Convert from phaseoffset_fs to register value */ - offset_regval = div_s64(offset_fs * 1000, IDT_T0DPLL_PHASE_RESOL); + offset_regval = div_s64((s64)(-offset_ns) * 1000000000ll, + IDT_T0DPLL_PHASE_RESOL); val[0] = offset_regval & 0xFF; val[1] = (offset_regval >> 8) & 0xFF;
@@ -1175,6 +1174,7 @@ static void idt82p33_caps_init(u32 index, struct ptp_clock_info *caps, caps->n_ext_ts = MAX_PHC_PLL, caps->n_pins = max_pins, caps->adjphase = idt82p33_adjwritephase, + caps->getmaxphase = idt82p33_getmaxphase, caps->adjfine = idt82p33_adjfine; caps->adjtime = idt82p33_adjtime; caps->gettime64 = idt82p33_gettime;
diff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h
index 8fcb0b17d207..6a63c14b6966 100644
--- a/drivers/ptp/ptp_idt82p33.h
+++ b/drivers/ptp/ptp_idt82p33.h@@ -43,9 +43,9 @@ #define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0 /** - * @brief Maximum absolute value for write phase offset in femtoseconds + * @brief Maximum absolute value for write phase offset in nanoseconds */ -#define WRITE_PHASE_OFFSET_LIMIT (20000052084ll) +#define WRITE_PHASE_OFFSET_LIMIT (20000l) /** @brief Phase offset resolution *
--
2.38.4