-----Original Message-----
From: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
Sent: Tuesday, February 14, 2023 9:49 AM
To: Veerasenareddy Burru <vburru@marvell.com>
Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; Abhijit Ayarekar
[off-list ref]; Sathesh B Edara [off-list ref];
Satananda Burla [off-list ref]; linux-doc@vger.kernel.org; David S.
Miller [off-list ref]; Eric Dumazet [off-list ref];
Jakub Kicinski [off-list ref]; Paolo Abeni [off-list ref]
Subject: [EXT] Re: [PATCH net-next v3 3/7] octeon_ep: control mailbox for
multiple PFs

External Email

----------------------------------------------------------------------
On Mon, Feb 13, 2023 at 09:14:18PM -0800, Veerasenareddy Burru wrote:

quoted

Add control mailbox support for multiple PFs.
Update control mbox base address calculation based on PF function link.

Signed-off-by: Veerasenareddy Burru <vburru@marvell.com>
Signed-off-by: Abhijit Ayarekar <redacted>
---
v2 -> v3:
 * no change

v1 -> v2:
 * no change

 .../ethernet/marvell/octeon_ep/octep_cn9k_pf.c   | 16

+++++++++++++++-

quoted

 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
index f40ebac15a79..c82a1347eed8 100644

--- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

@@ -13,6 +13,9 @@
 #include "octep_main.h"
 #include "octep_regs_cn9k_pf.h"

+#define CTRL_MBOX_MAX_PF	128
+#define CTRL_MBOX_SZ		((size_t)(0x400000 /

CTRL_MBOX_MAX_PF))

quoted

+
 /* Names of Hardware non-queue generic interrupts */  static char
*cn93_non_ioq_msix_names[] = {
 	"epf_ire_rint",

@@ -199,6 +202,8 @@ static void octep_init_config_cn93_pf(struct

octep_device *oct)

quoted

 	struct octep_config *conf = oct->conf;
 	struct pci_dev *pdev = oct->pdev;
 	u64 val;
+	int pos;
+	u8 link = 0;

RCT again

Very sorry for missing these before submitting; Will take care next time.

quoted

 	/* Read ring configuration:
 	 * PF ring count, number of VFs and rings per VF supported @@ -

234,7

quoted

+239,16 @@ static void octep_init_config_cn93_pf(struct octep_device

*oct)

quoted

 	conf->msix_cfg.ioq_msix = conf->pf_ring_cfg.active_io_rings;
 	conf->msix_cfg.non_ioq_msix_names =

cn93_non_ioq_msix_names;

quoted

-	conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct-
mmio[2].hw_addr + (0x400000ull * 7);
+	pos = pci_find_ext_capability(oct->pdev, PCI_EXT_CAP_ID_SRIOV);
+	if (pos) {
+		pci_read_config_byte(oct->pdev,
+				     pos + PCI_SRIOV_FUNC_LINK,
+				     &link);
+		link = PCI_DEVFN(PCI_SLOT(oct->pdev->devfn), link);
+	}
+	conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct-
mmio[2].hw_addr +
+					   (0x400000ull * 8) +

can you explain why s/7/8 and was it broken previously?

Thank you for the feedback.
Not broken; It works with 7.
It was an experimental change only; should not have been included in the upstream patch.
Will revert this change in next revision.

quoted

+					   (link * CTRL_MBOX_SZ);
 }

 /* Setup registers for a hardware Tx Queue  */
--
2.36.0