Re: [PATCH v3 01/19] dt-bindings: ARM: MediaTek: Add new document bindings of MT8188 clock

On Fri, 2022-12-30 at 11:41 +0100, Krzysztof Kozlowski wrote:

On 30/12/2022 08:33, Garmin.Chang wrote:

quoted

Add the new binding documentation for system clock
and functional clock on MediaTek MT8188.

Subject: drop second, redundant "document bindings of".

Hi Krzysztof,

Thank you for your suggestions.
OK. I'll remove it in v4.

quoted

Signed-off-by: Garmin.Chang <redacted>
---
 .../arm/mediatek/mediatek,mt8188-clock.yaml   |  71 ++
 .../mediatek/mediatek,mt8188-sys-clock.yaml   |  55 ++
 .../dt-bindings/clock/mediatek,mt8188-clk.h   | 733
++++++++++++++++++
 3 files changed, 859 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-
clock.yaml
 create mode 100644
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys-
clock.yaml
 create mode 100644 include/dt-bindings/clock/mediatek,mt8188-clk.h

diff --git
a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-
clock.yaml
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-
clock.yaml
new file mode 100644
index 000000000000..6654cead71f6

--- /dev/null
+++

b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-
clock.yaml

Clock controllers do not go to arm but to clock. It's so suprising
directory that I missed to notice it in v1... Why putting it in some
totally irrelevant directory?

Do you mean move to the path below ?
Documentation\devicetree\bindings\clock

If yes, I will change it in v4.

quoted

@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 

https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!k6TPgiSrp00ShwE2Y9vMUkqWmyDNXd1bN0X4IvM6MyyHj-YDg7q-2_LnG8CTdYdtmQrVLIi8Y1z_kHzKzw6xIr02lel3z8Y$ 
 
+$schema: 
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!k6TPgiSrp00ShwE2Y9vMUkqWmyDNXd1bN0X4IvM6MyyHj-YDg7q-2_LnG8CTdYdtmQrVLIi8Y1z_kHzKzw6xIr02_N--doc$ 
 
+
+title: MediaTek Functional Clock Controller for MT8188
+
+maintainers:
+  - Garmin Chang [off-list ref]
+
+description: |
+  The clock architecture in MediaTek like below
+  PLLs -->
+          dividers -->
+                      muxes
+                           -->
+                              clock gate
+
+  The devices provide clock gate control in different IP blocks.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8188-adsp-audio26m
+      - mediatek,mt8188-imp-iic-wrap-c
+      - mediatek,mt8188-imp-iic-wrap-en
+      - mediatek,mt8188-imp-iic-wrap-w
+      - mediatek,mt8188-mfgcfg
+      - mediatek,mt8188-vppsys0
+      - mediatek,mt8188-wpesys
+      - mediatek,mt8188-wpesys-vpp0
+      - mediatek,mt8188-vppsys1
+      - mediatek,mt8188-imgsys
+      - mediatek,mt8188-imgsys-wpe1
+      - mediatek,mt8188-imgsys-wpe2
+      - mediatek,mt8188-imgsys-wpe3
+      - mediatek,mt8188-imgsys1-dip-top
+      - mediatek,mt8188-imgsys1-dip-nr
+      - mediatek,mt8188-ipesys
+      - mediatek,mt8188-camsys
+      - mediatek,mt8188-camsys-rawa
+      - mediatek,mt8188-camsys-yuva
+      - mediatek,mt8188-camsys-rawb
+      - mediatek,mt8188-camsys-yuvb
+      - mediatek,mt8188-ccusys
+      - mediatek,mt8188-vdecsys-soc
+      - mediatek,mt8188-vdecsys
+      - mediatek,mt8188-vencsys
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@11283000 {
+        compatible = "mediatek,mt8188-imp-iic-wrap-c";
+        reg = <0x11283000 0x1000>;
+        #clock-cells = <1>;
+    };
+
diff --git
a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-
sys-clock.yaml
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-
sys-clock.yaml
new file mode 100644
index 000000000000..2b28df1ff895

--- /dev/null
+++

b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-
sys-clock.yaml

Wrong directory.

 follow the answer above.

quoted

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 

https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-sys-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!k6TPgiSrp00ShwE2Y9vMUkqWmyDNXd1bN0X4IvM6MyyHj-YDg7q-2_LnG8CTdYdtmQrVLIi8Y1z_kHzKzw6xIr02P0KcerI$ 
 
+$schema: 
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!k6TPgiSrp00ShwE2Y9vMUkqWmyDNXd1bN0X4IvM6MyyHj-YDg7q-2_LnG8CTdYdtmQrVLIi8Y1z_kHzKzw6xIr02_N--doc$ 
 
+
+title: MediaTek System Clock Controller for MT8188
+
+maintainers:
+  - Garmin Chang [off-list ref]
+
+description: |
+  The clock architecture in MediaTek like below
+  PLLs -->
+          dividers -->
+                      muxes
+                           -->
+                              clock gate
+
+  The apmixedsys provides most of PLLs which generated from SoC
26m.
+  The topckgen provides dividers and muxes which provide the clock
source to other IP blocks.
+  The infracfg_ao provides clock gate in peripheral and
infrastructure IP blocks.
+  The mcusys provides mux control to select the clock source in AP
MCU.
+  The device nodes also provide the system control capacity for
configuration.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8188-topckgen
+          - mediatek,mt8188-infracfg-ao
+          - mediatek,mt8188-apmixedsys
+          - mediatek,mt8188-pericfg-ao
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@10000000 {

clock-controller

OK. I'll use clock-controller in v4.

quoted

+        compatible = "mediatek,mt8188-topckgen", "syscon";
+        reg = <0x10000000 0x1000>;
+        #clock-cells = <1>;

Best regards,
Krzysztof