-----Original Message-----
From: Jakub Kicinski <kuba@kernel.org>
Sent: Friday, August 26, 2022 9:49 PM
To: David Thompson <davthompson@nvidia.com>
Cc: davem@davemloft.net; edumazet@google.com; pabeni@redhat.com;
netdev@vger.kernel.org; cai.huoqing@linux.dev; brgl@bgdev.pl; Liming Sun
[off-list ref]; Asmaa Mnebhi [off-list ref]
Subject: Re: [PATCH net v1] mlxbf_gige: compute MDIO period based on i1clk

On Fri, 26 Aug 2022 11:59:16 -0400 David Thompson wrote:

quoted

This patch adds logic to compute the MDIO period based on the i1clk,
and thereafter write the MDIO period into the YU MDIO config register.
The i1clk resource from the ACPI table is used to provide addressing
to YU bootrecord PLL registers.
The values in these registers are used to compute MDIO period.
If the i1clk resource is not present in the ACPI table, then the
current default hardcorded value of 430Mhz is used.
The i1clk clock value of 430MHz is only accurate for boards with BF2
mid bin and main bin SoCs. The BF2 high bin SoCs have i1clk = 500MHz,
but can support a slower MDIO period.

Fixes: f92e1869d74e ("Add Mellanox BlueField Gigabit Ethernet driver")
Reviewed-by: Asmaa Mnebhi <asmaa@nvidia.com>
Signed-off-by: David Thompson <davthompson@nvidia.com>

Hm, why did you repost this?

I reposted because the first post failed the "netdev/cc_maintainers" test:

	netdev/cc_maintainers	fail	1 blamed authors not CCed: limings@nvidia.com; 1 maintainers not CCed: limings@nvidia.com

In the second post I included "limings@nvidia.com" .

- Dave