From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-08-30 19:59:57
Those who have been following part 1:
https://patchwork.kernel.org/project/netdevbpf/cover/20220511095020.562461-1-vladimir.oltean@nxp.com/
part 2:
https://patchwork.kernel.org/project/netdevbpf/cover/20220521213743.2735445-1-vladimir.oltean@nxp.com/
and part 3:
https://patchwork.kernel.org/project/netdevbpf/cover/20220819174820.3585002-1-vladimir.oltean@nxp.com/
will know that I am trying to enable the second internal port pair from
the NXP LS1028A Felix switch for DSA-tagged traffic via "ocelot-8021q".
This series represents the final part of that effort. We have:
- the introduction of new UAPI in the form of IFLA_DSA_MASTER
- preparation for LAG DSA masters in terms of suppressing some
operations for masters in the DSA core that simply don't make sense
when those masters are a bonding/team interface
- handling all the net device events that occur between DSA and a
LAG DSA master, including migration to a different DSA master when the
current master joins a LAG, or the LAG gets destroyed
- updating documentation
- adding an implementation for NXP LS1028A, where things are insanely
complicated due to hardware limitations. We have 2 tagging protocols:
* the native "ocelot" protocol (NPI port mode). This does not support
CPU ports in a LAG, and supports a single DSA master. The DSA master
can be changed between eno2 (2.5G) and eno3 (1G), but all ports must
be down during the changing process, and user ports assigned to the
old DSA master will refuse to come up if the user requests that
during a "transient" state.
* the "ocelot-8021q" software-defined protocol, where the Ethernet
ports connected to the CPU are not actually "god mode" ports as far
as the hardware is concerned. So here, static assignment between
user and CPU ports is possible by editing the PGID_SRC masks for
the port-based forwarding matrix, and "CPU ports in a LAG" simply
means "a LAG like any other".
The series was regression-tested on LS1028A using the local_termination.sh
kselftest, in most of the possible operating modes and tagging protocols.
I have not done a detailed performance evaluation yet, but using LAG, is
possible to exceed the termination bandwidth of a single CPU port in an
iperf3 test with multiple senders and multiple receivers.
There was a previous RFC posted, which contains most of these changes,
however it's so old by now that it's unlikely anyone of the reviewers
remembers it in detail. I've applied most of the feedback requested by
Florian and Ansuel there.
https://lore.kernel.org/netdev/20220523104256.3556016-1-olteanv@gmail.com/
Vladimir Oltean (9):
net: introduce iterators over synced hw addresses
net: dsa: introduce dsa_port_get_master()
net: dsa: allow the DSA master to be seen and changed through
rtnetlink
net: dsa: don't keep track of admin/oper state on LAG DSA masters
net: dsa: suppress appending ethtool stats to LAG DSA masters
net: dsa: suppress device links to LAG DSA masters
net: dsa: allow masters to join a LAG
docs: net: dsa: update information about multiple CPU ports
net: dsa: felix: add support for changing DSA master
.../networking/dsa/configuration.rst | 84 +++++
Documentation/networking/dsa/dsa.rst | 38 ++-
drivers/net/dsa/bcm_sf2.c | 4 +-
drivers/net/dsa/bcm_sf2_cfp.c | 4 +-
drivers/net/dsa/lan9303-core.c | 4 +-
drivers/net/dsa/ocelot/felix.c | 117 ++++++-
drivers/net/dsa/ocelot/felix.h | 3 +
.../net/ethernet/mediatek/mtk_ppe_offload.c | 2 +-
drivers/net/ethernet/mscc/ocelot.c | 3 +-
include/linux/netdevice.h | 6 +
include/net/dsa.h | 19 ++
include/soc/mscc/ocelot.h | 1 +
include/uapi/linux/if_link.h | 10 +
net/dsa/Makefile | 10 +-
net/dsa/dsa.c | 9 +
net/dsa/dsa2.c | 34 ++-
net/dsa/dsa_priv.h | 17 +-
net/dsa/master.c | 82 ++++-
net/dsa/netlink.c | 62 ++++
net/dsa/port.c | 159 +++++++++-
net/dsa/slave.c | 288 +++++++++++++++++-
net/dsa/switch.c | 22 +-
net/dsa/tag_8021q.c | 4 +-
23 files changed, 924 insertions(+), 58 deletions(-)
create mode 100644 net/dsa/netlink.c
--
2.34.1
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-08-30 20:00:08
Some network drivers use __dev_mc_sync()/__dev_uc_sync() and therefore
program the hardware only with addresses with a non-zero sync_cnt.
Some of the above drivers also need to save/restore the address
filtering lists when certain events happen, and they need to walk
through the struct net_device :: uc and struct net_device :: mc lists.
But these lists contain unsynced addresses too.
To keep the appearance of an elementary form of data encapsulation,
provide iterators through these lists that only look at entries with a
non-zero sync_cnt, instead of filtering entries out from device drivers.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
include/linux/netdevice.h | 6 ++++++
1 file changed, 6 insertions(+)
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-08-30 20:00:37
There is a desire to support for DSA masters in a LAG.
That configuration is intended to work by simply enslaving the master to
a bonding/team device. But the physical DSA master (the LAG slave) still
has a dev->dsa_ptr, and that cpu_dp still corresponds to the physical
CPU port.
However, we would like to be able to retrieve the LAG that's the upper
of the physical DSA master. In preparation for that, introduce a helper
called dsa_port_get_master() that replaces all occurrences of the
dp->cpu_dp->master pattern. The distinction between LAG and non-LAG will
be made later within the helper itself.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/net/dsa/bcm_sf2.c | 4 +--
drivers/net/dsa/bcm_sf2_cfp.c | 4 +--
drivers/net/dsa/lan9303-core.c | 4 +--
.../net/ethernet/mediatek/mtk_ppe_offload.c | 2 +-
include/net/dsa.h | 5 ++++
net/dsa/dsa2.c | 8 +++---
net/dsa/dsa_priv.h | 2 +-
net/dsa/port.c | 28 +++++++++----------
net/dsa/slave.c | 11 ++++----
net/dsa/tag_8021q.c | 4 +--
10 files changed, 38 insertions(+), 34 deletions(-)
@@ -1102,7 +1102,7 @@ static int bcm_sf2_cfp_rule_get_all(struct bcm_sf2_priv *priv,intbcm_sf2_get_rxnfc(structdsa_switch*ds,intport,structethtool_rxnfc*nfc,u32*rule_locs){-structnet_device*p=dsa_to_port(ds,port)->cpu_dp->master;+structnet_device*p=dsa_port_to_master(dsa_to_port(ds,port));structbcm_sf2_priv*priv=bcm_sf2_to_priv(ds);intret=0;
@@ -1145,7 +1145,7 @@ int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,intbcm_sf2_set_rxnfc(structdsa_switch*ds,intport,structethtool_rxnfc*nfc){-structnet_device*p=dsa_to_port(ds,port)->cpu_dp->master;+structnet_device*p=dsa_port_to_master(dsa_to_port(ds,port));structbcm_sf2_priv*priv=bcm_sf2_to_priv(ds);intret=0;
@@ -322,7 +322,7 @@ dsa_slave_to_master(const struct net_device *dev){structdsa_port*dp=dsa_slave_to_port(dev);-returndp->cpu_dp->master;+returndsa_port_to_master(dp);}/* If under a bridge with vlan_filtering=0, make sure to send pvid-tagged
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-08-30 20:00:43
We store information about the DSA master's state in
cpu_dp->master_admin_up and cpu_dp->master_oper_up, and this assumes a
bijective association between a CPU port and a DSA master.
However, when we have CPU ports in a LAG (and DSA masters in a LAG too),
the way in which we set up things is that the physical DSA masters still
have dev->dsa_ptr pointing to our cpu_dp, but the bonding/team device
itself also has its dev->dsa_ptr pointing towards one of the CPU port
structures (the first one).
So logically speaking, that first cpu_dp can't keep track of both the
physical master's admin/oper state, and of the bonding master's state.
This isn't even needed; the reason why we keep track of the DSA master's
state is to know when it is available for Ethernet-based register access.
For that use case, we don't even need LAG; we just need to decide upon
one of the physical DSA masters (if there is more than 1 available) and
use that.
This change suppresses dsa_tree_master_{admin,oper}_state_change() calls
on LAG DSA masters (which will be supported in a future change), to
allow the tracking of just physical DSA masters.
Link: https://lore.kernel.org/netdev/628cc94d.1c69fb81.15b0d.422d@mx.google.com/
Suggested-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
net/dsa/dsa2.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
@@ -1326,6 +1326,12 @@ void dsa_tree_master_admin_state_change(struct dsa_switch_tree *dst,structdsa_port*cpu_dp=master->dsa_ptr;boolnotify=false;+/* Don't keep track of admin state on LAG DSA masters,+*butratherjustofphysicalDSAmasters+*/+if(netif_is_lag_master(master))+return;+if((dsa_port_master_is_operational(cpu_dp))!=(up&&cpu_dp->master_oper_up))notify=true;
@@ -1343,6 +1349,12 @@ void dsa_tree_master_oper_state_change(struct dsa_switch_tree *dst,structdsa_port*cpu_dp=master->dsa_ptr;boolnotify=false;+/* Don't keep track of oper state on LAG DSA masters,+*butratherjustofphysicalDSAmasters+*/+if(netif_is_lag_master(master))+return;+if((dsa_port_master_is_operational(cpu_dp))!=(cpu_dp->master_admin_up&&up))notify=true;
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-08-30 20:00:59
Some DSA switches have multiple CPU ports, which can be used to improve
CPU termination throughput, but DSA, through dsa_tree_setup_cpu_ports(),
sets up only the first one, leading to suboptimal use of hardware.
The desire is to not change the default configuration but to permit the
user to create a dynamic mapping between individual user ports and the
CPU port that they are served by, configurable through rtnetlink. It is
also intended to permit load balancing between CPU ports, and in that
case, the foreseen model is for the DSA master to be a bonding interface
whose lowers are the physical DSA masters.
To that end, we create a struct rtnl_link_ops for DSA user ports with
the "dsa" kind. We expose the IFLA_DSA_MASTER link attribute that
contains the ifindex of the newly desired DSA master.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
include/net/dsa.h | 8 +++
include/uapi/linux/if_link.h | 10 +++
net/dsa/Makefile | 10 ++-
net/dsa/dsa.c | 9 +++
net/dsa/dsa2.c | 14 ++++
net/dsa/dsa_priv.h | 10 +++
net/dsa/netlink.c | 62 +++++++++++++++++
net/dsa/port.c | 131 +++++++++++++++++++++++++++++++++++
net/dsa/slave.c | 120 ++++++++++++++++++++++++++++++++
9 files changed, 373 insertions(+), 1 deletion(-)
create mode 100644 net/dsa/netlink.c
@@ -387,6 +387,20 @@ static struct dsa_port *dsa_tree_find_first_cpu(struct dsa_switch_tree *dst)returnNULL;}+structnet_device*dsa_tree_find_first_master(structdsa_switch_tree*dst)+{+structdevice_node*ethernet;+structnet_device*master;+structdsa_port*cpu_dp;++cpu_dp=dsa_tree_find_first_cpu(dst);+ethernet=of_parse_phandle(cpu_dp->dn,"ethernet",0);+master=of_find_net_device_by_node(ethernet);+of_node_put(ethernet);++returnmaster;+}+/* Assign the default CPU port (the first one in the tree) to all ports of the*fabricwhichdon'talreadyhaveoneaspartoftheirownswitch.*/
@@ -1374,6 +1375,136 @@ int dsa_port_mrp_del_ring_role(const struct dsa_port *dp,returnds->ops->port_mrp_del_ring_role(ds,dp->index,mrp);}+staticintdsa_port_assign_master(structdsa_port*dp,+structnet_device*master,+structnetlink_ext_ack*extack,+boolfail_on_err)+{+structdsa_switch*ds=dp->ds;+intport=dp->index,err;++err=ds->ops->port_change_master(ds,port,master,extack);+if(err&&!fail_on_err)+dev_err(ds->dev,"port %d failed to assign master %s: %pe\n",+port,master->name,ERR_PTR(err));++if(err&&fail_on_err)+returnerr;++dp->cpu_dp=master->dsa_ptr;++return0;+}++/* Change the dp->cpu_dp affinity for a user port. Note that both cross-chip+*notifiersanddrivershaveimplicitassumptionsaboutuser-to-CPU-port+*mappings,soweunfortunatelycannotdelaythedeletionoftheobjects+*(switchdev,standaloneaddresses,standaloneVLANs)ontheoldCPUport+*untilthenewCPUporthasbeensetup.Soweneedtocompletelyteardown+*theoldCPUportbeforechangingit,andrestoreitonerrorsduringthe+*bringupofthenewone.+*/+intdsa_port_change_master(structdsa_port*dp,structnet_device*master,+structnetlink_ext_ack*extack)+{+structnet_device*bridge_dev=dsa_port_bridge_dev_get(dp);+structnet_device*old_master=dsa_port_to_master(dp);+structnet_device*dev=dp->slave;+structdsa_switch*ds=dp->ds;+intport=dp->index;+boolvlan_filtering;+interr,tmp;++/* Bridges may hold host FDB, MDB and VLAN objects. These need to be+*migrated,sodynamicallyunoffloadandlaterreoffloadthebridge+*port.+*/+if(bridge_dev){+dsa_port_pre_bridge_leave(dp,bridge_dev);+dsa_port_bridge_leave(dp,bridge_dev);+}++/* The port might still be VLAN filtering even if it's no longer+*underabridge,eitherduetods->vlan_filtering_is_globalor+*ds->needs_standalone_vlan_filtering.InturnthismeansVLANs+*ontheCPUport.+*/+vlan_filtering=dsa_port_is_vlan_filtering(dp);+if(vlan_filtering){+err=dsa_slave_manage_vlan_filtering(dev,false);+if(err){+NL_SET_ERR_MSG_MOD(extack,+"Failed to remove standalone VLANs");+gotorewind_old_bridge;+}+}++/* Standalone addresses, and addresses of upper interfaces like+*VLAN,LAG,HSRneedtobemigrated.+*/+dsa_slave_unsync_ha(dev);++err=dsa_port_assign_master(dp,master,extack,true);+if(err)+gotorewind_old_addrs;++dsa_slave_sync_ha(dev);++if(vlan_filtering){+err=dsa_slave_manage_vlan_filtering(dev,true);+if(err){+NL_SET_ERR_MSG_MOD(extack,+"Failed to restore standalone VLANs");+gotorewind_new_addrs;+}+}++if(bridge_dev){+err=dsa_port_bridge_join(dp,bridge_dev,extack);+if(err&&err==-EOPNOTSUPP){+NL_SET_ERR_MSG_MOD(extack,+"Failed to reoffload bridge");+gotorewind_new_vlan;+}+}++return0;++rewind_new_vlan:+if(vlan_filtering)+dsa_slave_manage_vlan_filtering(dev,false);++rewind_new_addrs:+dsa_slave_unsync_ha(dev);++dsa_port_assign_master(dp,old_master,NULL,false);++/* Restore the objects on the old CPU port */+rewind_old_addrs:+dsa_slave_sync_ha(dev);++if(vlan_filtering){+tmp=dsa_slave_manage_vlan_filtering(dev,true);+if(tmp){+dev_err(ds->dev,+"port %d failed to restore standalone VLANs: %pe\n",+dp->index,ERR_PTR(tmp));+}+}++rewind_old_bridge:+if(bridge_dev){+tmp=dsa_port_bridge_join(dp,bridge_dev,extack);+if(tmp){+dev_err(ds->dev,+"port %d failed to rejoin bridge %s: %pe\n",+dp->index,bridge_dev->name,ERR_PTR(tmp));+}+}++returnerr;+}+voiddsa_port_set_tag_protocol(structdsa_port*cpu_dp,conststructdsa_device_ops*tag_ops){
@@ -2346,6 +2388,7 @@ int dsa_slave_create(struct dsa_port *port)if(slave_dev==NULL)return-ENOMEM;+slave_dev->rtnl_link_ops=&dsa_link_ops;slave_dev->ethtool_ops=&dsa_slave_ethtool_ops;#if IS_ENABLED(CONFIG_DCB)slave_dev->dcbnl_ops=&dsa_slave_dcbnl_ops;
@@ -2462,6 +2505,83 @@ void dsa_slave_destroy(struct net_device *slave_dev)free_netdev(slave_dev);}+intdsa_slave_change_master(structnet_device*dev,structnet_device*master,+structnetlink_ext_ack*extack)+{+structnet_device*old_master=dsa_slave_to_master(dev);+structdsa_port*dp=dsa_slave_to_port(dev);+structdsa_switch*ds=dp->ds;+structnet_device*upper;+structlist_head*iter;+interr;++if(master==old_master)+return0;++if(!ds->ops->port_change_master){+NL_SET_ERR_MSG_MOD(extack,+"Driver does not support changing DSA master");+return-EOPNOTSUPP;+}++if(!netdev_uses_dsa(master)){+NL_SET_ERR_MSG_MOD(extack,+"Interface not eligible as DSA master");+return-EOPNOTSUPP;+}++netdev_for_each_upper_dev_rcu(master,upper,iter){+if(dsa_slave_dev_check(upper))+continue;+if(netif_is_bridge_master(upper))+continue;+NL_SET_ERR_MSG_MOD(extack,"Cannot join master with unknown uppers");+return-EOPNOTSUPP;+}++/* Since we allow live-changing the DSA master, plus we auto-open the+*DSAmasterwhentheuserportopens=>weneedtoensurethatthe+*newDSAmasterisopentoo.+*/+if(dev->flags&IFF_UP){+err=dev_open(master,extack);+if(err)+returnerr;+}++netdev_upper_dev_unlink(old_master,dev);++err=netdev_upper_dev_link(master,dev,extack);+if(err)+gotoout_revert_old_master_unlink;++err=dsa_port_change_master(dp,master,extack);+if(err)+gotoout_revert_master_link;++/* Update the MTU of the new CPU port through cross-chip notifiers */+err=dsa_slave_change_mtu(dev,dev->mtu);+if(err&&err!=-EOPNOTSUPP){+netdev_warn(dev,+"nonfatal error updating MTU with new master: %pe\n",+ERR_PTR(err));+}++/* If the port doesn't have its own MAC address and relies on the DSA+*master'sone,inherititagainfromthenewDSAmaster.+*/+if(is_zero_ether_addr(dp->mac))+eth_hw_addr_inherit(dev,master);++return0;++out_revert_master_link:+netdev_upper_dev_unlink(master,dev);+out_revert_old_master_unlink:+netdev_upper_dev_link(old_master,dev,NULL);+returnerr;+}+booldsa_slave_dev_check(conststructnet_device*dev){returndev->netdev_ops==&dsa_slave_netdev_ops;
From: Jakub Kicinski <kuba@kernel.org> Date: 2022-09-01 03:50:31
On Tue, 30 Aug 2022 22:59:26 +0300 Vladimir Oltean wrote:
Some DSA switches have multiple CPU ports, which can be used to improve
CPU termination throughput, but DSA, through dsa_tree_setup_cpu_ports(),
sets up only the first one, leading to suboptimal use of hardware.
The desire is to not change the default configuration but to permit the
user to create a dynamic mapping between individual user ports and the
CPU port that they are served by, configurable through rtnetlink. It is
also intended to permit load balancing between CPU ports, and in that
case, the foreseen model is for the DSA master to be a bonding interface
whose lowers are the physical DSA masters.
To that end, we create a struct rtnl_link_ops for DSA user ports with
the "dsa" kind. We expose the IFLA_DSA_MASTER link attribute that
contains the ifindex of the newly desired DSA master.
net/dsa/port.c: In function ‘dsa_port_change_master’:
net/dsa/port.c:1414:13: warning: unused variable ‘port’ [-Wunused-variable]
1414 | int port = dp->index;
| ^~~~
I presume you had a look around what side effects setting rtnl_link_ops
will have? Should .netns_refund be true?
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-09-01 13:33:08
On Wed, Aug 31, 2022 at 08:50:20PM -0700, Jakub Kicinski wrote:
net/dsa/port.c: In function ‘dsa_port_change_master’:
net/dsa/port.c:1414:13: warning: unused variable ‘port’ [-Wunused-variable]
1414 | int port = dp->index;
| ^~~~
I did build patch by patch, but in the sea of stuff that got rebuilt
when I modified include/uapi/linux/if_link.h, I couldn't notice anything.
I presume you had a look around what side effects setting rtnl_link_ops
will have? Should .netns_refund be true?
I'm not quite sure what other side effects there will be. The netns_refund
property should be set to true, yes.
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-08-30 20:01:05
Similar to the discussion about tracking the admin/oper state of LAG DSA
masters, we have the problem here that struct dsa_port *cpu_dp caches a
single pair of orig_ethtool_ops and netdev_ops pointers.
So if we call dsa_master_setup(bond0, cpu_dp) where cpu_dp is also the
dev->dsa_ptr of one of the physical DSA masters, we'd effectively
overwrite what we cached from that physical netdev with what replaced
from the bonding interface.
We don't need DSA ethtool stats on the bonding interface when used as
DSA master, it's good enough to have them just on the physical DSA
masters, so suppress this logic.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
net/dsa/master.c | 9 +++++++++
1 file changed, 9 insertions(+)
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-08-30 20:01:22
These don't work (print a harmless error about the operation failing)
and make little sense to have anyway, because when a LAG DSA master goes
away, we will introduce logic to move our CPU port back to the first
physical DSA master. So suppress these device links in preparation for
adding support for LAG DSA masters.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
net/dsa/master.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
@@ -364,12 +364,14 @@ int dsa_master_setup(struct net_device *dev, struct dsa_port *cpu_dp)mtu=ETH_DATA_LEN+dsa_tag_protocol_overhead(tag_ops);/* The DSA master must use SET_NETDEV_DEV for this to work. */-consumer_link=device_link_add(ds->dev,dev->dev.parent,-DL_FLAG_AUTOREMOVE_CONSUMER);-if(!consumer_link)-netdev_err(dev,-"Failed to create a device link to DSA switch %s\n",-dev_name(ds->dev));+if(!netif_is_lag_master(dev)){+consumer_link=device_link_add(ds->dev,dev->dev.parent,+DL_FLAG_AUTOREMOVE_CONSUMER);+if(!consumer_link)+netdev_err(dev,+"Failed to create a device link to DSA switch %s\n",+dev_name(ds->dev));+}/* The switch driver may not implement ->port_change_mtu(), case in*whichdsa_slave_change_mtu()willnotupdatethemasterMTUeither,
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-08-30 20:01:39
There are 2 ways in which a DSA user port may become handled by 2 CPU
ports in a LAG:
(1) its current DSA master joins a LAG
ip link del bond0 && ip link add bond0 type bond mode 802.3ad
ip link set eno2 master bond0
When this happens, all user ports with "eno2" as DSA master get
automatically migrated to "bond0" as DSA master.
(2) it is explicitly configured as such by the user
# Before, the DSA master was eno3
ip link set swp0 type dsa master bond0
The design of this configuration is that the LAG device dynamically
becomes a DSA master through dsa_master_setup() when the first physical
DSA master becomes a LAG slave, and stops being so through
dsa_master_teardown() when the last physical DSA master leaves.
A LAG interface is considered as a valid DSA master only if it contains
existing DSA masters, and no other lower interfaces. Therefore, we
mainly rely on method (1) to enter this configuration.
Each physical DSA master (LAG slave) retains its dev->dsa_ptr for when
it becomes a standalone DSA master again. But the LAG master also has a
dev->dsa_ptr, and this is actually duplicated from one of the physical
LAG slaves, and therefore needs to be balanced when LAG slaves come and
go.
To the switch driver, putting DSA masters in a LAG is seen as putting
their associated CPU ports in a LAG.
We need to prepare cross-chip host FDB notifiers for CPU ports in a LAG,
by calling the driver's ->lag_fdb_add method rather than ->port_fdb_add.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
include/net/dsa.h | 6 ++
net/dsa/dsa_priv.h | 5 ++
net/dsa/master.c | 59 +++++++++++++++++
net/dsa/port.c | 2 +-
net/dsa/slave.c | 157 +++++++++++++++++++++++++++++++++++++++++++--
net/dsa/switch.c | 22 +++++--
6 files changed, 242 insertions(+), 9 deletions(-)
@@ -300,6 +300,9 @@ struct dsa_port {u8master_admin_up:1;u8master_oper_up:1;+/* Valid only on user ports */+u8cpu_port_in_lag:1;+u8setup:1;structdevice_node*dn;
@@ -428,3 +428,62 @@ void dsa_master_teardown(struct net_device *dev)*/wmb();}++intdsa_master_lag_setup(structnet_device*lag_dev,structdsa_port*cpu_dp,+structnetdev_lag_upper_info*uinfo,+structnetlink_ext_ack*extack)+{+boolmaster_setup=false;+structnet_device*lower;+structlist_head*iter;+interr;++/* To be eligible as a DSA master, a LAG must have all lower+*interfacesbeeligibleDSAmasters.+*/+netdev_for_each_lower_dev(lag_dev,lower,iter){+if(!netdev_uses_dsa(lower)){+NL_SET_ERR_MSG_MOD(extack,+"All LAG ports must be eligible as DSA masters");+return-EINVAL;+}+}++if(!netdev_uses_dsa(lag_dev)){+err=dsa_master_setup(lag_dev,cpu_dp);+if(err)+returnerr;+}++err=dsa_port_lag_join(cpu_dp,lag_dev,uinfo,extack);+if(err){+NL_SET_ERR_MSG_MOD(extack,+"CPU port failed to join LAG");+gotoout_master_teardown;+}++return0;++out_master_teardown:+if(master_setup)+dsa_master_teardown(lag_dev);+returnerr;+}++/* Tear down a master if there isn't any other user port on it,+*optionallyalsodestroyingLAGinformation.+*/+voiddsa_master_lag_teardown(structnet_device*lag_dev,+structdsa_port*cpu_dp)+{+structnet_device*upper;+structlist_head*iter;++dsa_port_lag_leave(cpu_dp,lag_dev);++netdev_for_each_upper_dev_rcu(lag_dev,upper,iter)+if(dsa_slave_dev_check(upper))+return;++dsa_master_teardown(lag_dev);+}
@@ -2887,6 +2891,138 @@ dsa_bridge_prechangelower_sanity_check(struct net_device *new_lower,returnNOTIFY_DONE;}+staticvoiddsa_tree_migrate_ports_from_lag_master(structdsa_switch_tree*dst,+structnet_device*lag_dev)+{+structnet_device*new_master;+structdsa_port*dp;+interr;++new_master=dsa_tree_find_first_master(dst);++dsa_tree_for_each_user_port(dp,dst){+if(dsa_port_to_master(dp)!=lag_dev)+continue;++err=dsa_slave_change_master(dp->slave,new_master,NULL);+if(err){+netdev_err(dp->slave,+"failed to restore master to %s: %pe\n",+new_master->name,ERR_PTR(err));+}+}+}++staticintdsa_master_lag_join(structnet_device*master,+structnet_device*lag_dev,+structnetdev_lag_upper_info*uinfo,+structnetlink_ext_ack*extack)+{+structdsa_port*cpu_dp=master->dsa_ptr;+structdsa_switch_tree*dst=cpu_dp->dst;+structdsa_port*dp;+interr;++err=dsa_master_lag_setup(lag_dev,cpu_dp,uinfo,extack);+if(err)+returnerr;++dsa_tree_for_each_user_port(dp,dst){+if(dsa_port_to_master(dp)!=master)+continue;++err=dsa_slave_change_master(dp->slave,lag_dev,extack);+if(err)+gotorestore;+}++return0;++restore:+dsa_tree_for_each_user_port_continue_reverse(dp,dst){+if(dsa_port_to_master(dp)!=lag_dev)+continue;++err=dsa_slave_change_master(dp->slave,master,NULL);+if(err){+netdev_err(dp->slave,+"failed to restore master to %s: %pe\n",+master->name,ERR_PTR(err));+}+}++dsa_master_lag_teardown(lag_dev,master->dsa_ptr);++returnerr;+}++staticvoiddsa_master_lag_leave(structnet_device*master,+structnet_device*lag_dev)+{+structdsa_port*dp,*cpu_dp=lag_dev->dsa_ptr;+structdsa_switch_tree*dst=cpu_dp->dst;+structdsa_port*new_cpu_dp=NULL;+structnet_device*lower;+structlist_head*iter;++netdev_for_each_lower_dev(lag_dev,lower,iter){+if(netdev_uses_dsa(lower)){+new_cpu_dp=lower->dsa_ptr;+break;+}+}++if(new_cpu_dp){+/* Update the CPU port of the user ports still under the LAG+*sothatdsa_port_to_master()continuestoworkproperly+*/+dsa_tree_for_each_user_port(dp,dst)+if(dsa_port_to_master(dp)==lag_dev)+dp->cpu_dp=new_cpu_dp;++/* Update the index of the virtual CPU port to match the lowest+*physicalCPUport+*/+lag_dev->dsa_ptr=new_cpu_dp;+wmb();+}else{+/* If the LAG DSA master has no ports left, migrate back all+*userportstothefirstphysicalCPUport+*/+dsa_tree_migrate_ports_from_lag_master(dst,lag_dev);+}++/* This DSA master has left its LAG in any case, so let+*theCPUportleavethehardwareLAGaswell+*/+dsa_master_lag_teardown(lag_dev,master->dsa_ptr);+}++staticintdsa_master_changeupper(structnet_device*dev,+structnetdev_notifier_changeupper_info*info)+{+structnetlink_ext_ack*extack;+interr=NOTIFY_DONE;++if(!netdev_uses_dsa(dev))+returnerr;++extack=netdev_notifier_info_to_extack(&info->info);++if(netif_is_lag_master(info->upper_dev)){+if(info->linking){+err=dsa_master_lag_join(dev,info->upper_dev,+info->upper_info,extack);+err=notifier_from_errno(err);+}else{+dsa_master_lag_leave(dev,info->upper_dev);+err=NOTIFY_OK;+}+}++returnerr;+}+staticintdsa_slave_netdevice_event(structnotifier_block*nb,unsignedlongevent,void*ptr){
@@ -2930,6 +3066,10 @@ static int dsa_slave_netdevice_event(struct notifier_block *nb,if(notifier_to_errno(err))returnerr;+err=dsa_master_changeupper(dev,ptr);+if(notifier_to_errno(err))+returnerr;+break;}caseNETDEV_CHANGELOWERSTATE:{
@@ -2937,12 +3077,21 @@ static int dsa_slave_netdevice_event(struct notifier_block *nb,structdsa_port*dp;interr;-if(!dsa_slave_dev_check(dev))-break;+if(dsa_slave_dev_check(dev)){+dp=dsa_slave_to_port(dev);++err=dsa_port_lag_change(dp,info->lower_state_info);+}-dp=dsa_slave_to_port(dev);+/* Mirror LAG port events on DSA masters that are in+*aLAGtowardstheirrespectiveswitchCPUports+*/+if(netdev_uses_dsa(dev)){+dp=dev->dsa_ptr;++err=dsa_port_lag_change(dp,info->lower_state_info);+}-err=dsa_port_lag_change(dp,info->lower_state_info);returnnotifier_from_errno(err);}caseNETDEV_CHANGE:
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-08-30 20:01:44
DSA now supports multiple CPU ports, explain the use cases that are
covered, the new UAPI, the permitted degrees of freedom, the driver API,
and remove some old "hanging fruits".
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
.../networking/dsa/configuration.rst | 84 +++++++++++++++++++
Documentation/networking/dsa/dsa.rst | 38 +++++++--
2 files changed, 116 insertions(+), 6 deletions(-)
@@ -49,6 +49,9 @@ In this documentation the following Ethernet interfaces are used:*eth0* the master interface+*eth1*+ another master interface, by default unused+*lan1* a slave interface
@@ -360,3 +363,84 @@ the ``self`` flag) has been removed. This results in the following changes: Script writers are therefore encouraged to use the ``master static`` set of flags when working with bridge FDB entries on DSA switch interfaces.++Affinity of user ports to CPU ports+-----------------------------------++Typically, DSA switches are attached to the host via a single Ethernet+interface, but in cases where the switch chip is discrete, the hardware design+may permit the use of 2 or more ports connected to the host, for an increase in+termination throughput.++DSA can make use of multiple CPU ports in two ways. First, it is possible to+statically assign the termination traffic associated with a certain user port+to be processed by a certain CPU port. This way, user space can implement+custom policies of static load balancing between user ports, by spreading the+affinities according to the available CPU ports.++Secondly, it is possible to perform load balancing between CPU ports on a per+packet basis, rather than statically assigning user ports to CPU ports.+This can be achieved by placing the DSA masters under a LAG interface (bonding+or team). DSA monitors this operation and creates a mirror of this software LAG+on the CPU ports facing the physical DSA masters that constitute the LAG slave+devices.++To make use of multiple CPU ports, the firmware (device tree) description of+the switch must mark all the links between CPU ports and their DSA masters+using the ``ethernet`` reference/phandle. At startup, only a single CPU port+and DSA master will be used - the numerically first port from the firmware+description which has an ``ethernet`` property. It is up to the user to+configure the system for the switch to use other masters.++DSA uses the ``rtnl_link_ops`` mechanism (with a "dsa" ``kind``) to allow+changing the DSA master of a user port. The ``IFLA_DSA_MASTER`` u32 netlink+attribute contains the ifindex of the master device that handles each slave+device. The DSA master must be a valid candidate based on firmware node+information, or a LAG interface which contains only slaves which are valid+candidates.++Using iproute2, the following manipulations are possible:++ ..code-block:: sh++ # See the DSA master in current use+ ip -d link show dev swp0+ (...)+ dsa master eth0++ # Static CPU port distribution+ ip link set swp0 type dsa master eth1+ ip link set swp1 type dsa master eth0+ ip link set swp2 type dsa master eth1+ ip link set swp3 type dsa master eth0++ # CPU ports in LAG+ ip link add bond0 type bond mode balance-xor && ip link set bond0 up+ ip link set eth0 down && ip link set eth0 master bond0+ ip link set eth1 down && ip link set eth1 master bond0+ ip -d link show dev swp0+ (...)+ dsa master bond0++Notice that in the case of CPU ports under a LAG, the use of the+``IFLA_DSA_MASTER`` netlink attribute is not strictly needed, but rather, DSA+reacts to the ``IFLA_MASTER`` attribute change of its present master (``eth0``)+and migrates all user ports to the new upper of ``eth0``, ``bond0``. Similarly,+when ``bond0`` is destroyed using ``RTM_DELLINK``, DSA migrates the user ports+that were assigned to this interface to the first physical DSA master which is+eligible, based on the firmware description (it effectively reverts to the+startup configuration).++In a setup with more than 2 physical CPU ports, it is therefore possible to mix+static user to CPU port assignment with LAG between DSA masters. It is not+possible to statically assign a user port towards a DSA master that has any+upper interfaces (this includes LAG devices - the master must always be the LAG+in this case).++Live changing of the DSA master (and thus CPU port) affinity of a user port is+permitted, in order to allow dynamic redistribution in response to traffic.++Physical DSA masters are allowed to join and leave at any time a LAG interface+used as a DSA master; however, DSA will reject a LAG interface as a valid+candidate for being a DSA master unless it has at least one physical DSA master+as a slave device.
@@ -303,6 +303,20 @@ These frames are then queued for transmission using the master network device Ethernet switch will be able to process these incoming frames from the management interface and deliver them to the physical switch port.+When using multiple CPU ports, it is possible to stack a LAG (bonding/team)+device between the DSA slave devices and the physical DSA masters. The LAG+device is thus also a DSA master, but the LAG slave devices continue to be DSA+masters as well (just with no user port assigned to them; this is needed for+recovery in case the LAG DSA master disappears). Thus, the data path of the LAG+DSA master is used asymmetrically. On RX, the ``ETH_P_XDSA`` handler, which+calls ``dsa_switch_rcv()``, is invoked early (on the physical DSA master;+LAG slave). Therefore, the RX data path of the LAG DSA master is not used.+On the other hand, TX takes place linearly: ``dsa_slave_xmit`` calls+``dsa_enqueue_skb``, which calls ``dev_queue_xmit`` towards the LAG DSA master.+The latter calls ``dev_queue_xmit`` towards one physical DSA master or the+other, and in both cases, the packet exits the system through a hardware path+towards the switch.+ Graphical representation ------------------------
@@ -629,6 +643,24 @@ Switch configuration PHY cannot be found. In this case, probing of the DSA switch continues without that particular port.+-``port_change_master``: method through which the affinity (association used+ for traffic termination purposes) between a user port and a CPU port can be+ changed. By default all user ports from a tree are assigned to the first+ available CPU port that makes sense for them (most of the times this means+ the user ports of a tree are all assigned to the same CPU port, except for H+ topologies as described in commit 2c0b03258b8b). The ``port`` argument+ represents the index of the user port, and the ``master`` argument represents+ the new DSA master ``net_device``. The CPU port associated with the new+ master can be retrieved by looking at ``struct dsa_port *cpu_dp =+ master->dsa_ptr``. Additionally, the master can also be a LAG device where+ all the slave devices are physical DSA masters. LAG DSA masters also have a+ valid ``master->dsa_ptr`` pointer, however this is not unique, but rather a+ duplicate of the first physical DSA master's (LAG slave) ``dsa_ptr``. In case+ of a LAG DSA master, a further call to ``port_lag_join`` will be emitted+ separately for the physical CPU ports associated with the physical DSA+ masters, requesting them to create a hardware LAG associated with the LAG+ interface.+ PHY devices and link management -------------------------------
@@ -1095,9 +1127,3 @@ capable hardware, but does not enforce a strict switch device driver model. On the other DSA enforces a fairly strict device driver model, and deals with most of the switch specific. At some point we should envision a merger between these two subsystems and get the best of both worlds.--Other hanging fruits------------------------ allowing more than one CPU/management interface:- http://comments.gmane.org/gmane.linux.network/365657
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-08-30 20:01:54
Changing the DSA master means different things depending on the tagging
protocol in use.
For NPI mode ("ocelot" and "seville"), there is a single port which can
be configured as NPI, but DSA only permits changing the CPU port
affinity of user ports one by one. So changing a user port to a
different NPI port globally changes what the NPI port is, and breaks the
user ports still using the old one.
To address this while still permitting the change of the NPI port,
require that the user ports which are still affine to the old NPI port
are down, and cannot be brought up until they are all affine to the same
NPI port.
The tag_8021q mode ("ocelot-8021q") is more flexible, in that each user
port can be freely assigned to one CPU port or to the other. This works
by filtering host addresses towards both tag_8021q CPU ports, and then
restricting the forwarding from a certain user port only to one of the
two tag_8021q CPU ports.
Additionally, the 2 tag_8021q CPU ports can be placed in a LAG. This
works by enabling forwarding via PGID_SRC from a certain user port
towards the logical port ID containing both tag_8021q CPU ports, but
then restricting forwarding per packet, via the LAG hash codes in
PGID_AGGR, to either one or the other.
When we change the DSA master to a LAG device, DSA guarantees us that
the LAG has at least one lower interface as a physical DSA master.
But DSA masters can come and go as lowers of that LAG, and
ds->ops->port_change_master() will not get called, because the DSA
master is still the same (the LAG). So we need to hook into the
ds->ops->port_lag_{join,leave} calls on the CPU ports and update the
logical port ID of the LAG that user ports are assigned to.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/dsa/ocelot/felix.c | 117 ++++++++++++++++++++++++++++-
drivers/net/dsa/ocelot/felix.h | 3 +
drivers/net/ethernet/mscc/ocelot.c | 3 +-
include/soc/mscc/ocelot.h | 1 +
4 files changed, 121 insertions(+), 3 deletions(-)
@@ -42,6 +42,25 @@ static struct net_device *felix_classify_db(struct dsa_db db)}}+staticintfelix_cpu_port_for_master(structdsa_switch*ds,+structnet_device*master)+{+structocelot*ocelot=ds->priv;+structdsa_port*cpu_dp;+intlag;++if(netif_is_lag_master(master)){+mutex_lock(&ocelot->fwd_domain_lock);+lag=ocelot_bond_get_id(ocelot,master);+mutex_unlock(&ocelot->fwd_domain_lock);++returnlag;+}++cpu_dp=master->dsa_ptr;+returncpu_dp->index;+}+/* Set up VCAP ES0 rules for pushing a tag_8021q VLAN towards the CPU such that*thetaggercanperformRXsourceportidentification.*/
@@ -422,6 +441,39 @@ static unsigned long felix_tag_npi_get_host_fwd_mask(struct dsa_switch *ds)returnBIT(ocelot->num_phys_ports);}+staticintfelix_tag_npi_change_master(structdsa_switch*ds,intport,+structnet_device*master,+structnetlink_ext_ack*extack)+{+structdsa_port*dp=dsa_to_port(ds,port),*other_dp;+structocelot*ocelot=ds->priv;++if(netif_is_lag_master(master)){+NL_SET_ERR_MSG_MOD(extack,"LAG DSA master only supported using ocelot-8021q");+return-EOPNOTSUPP;+}++/* Changing the NPI port breaks user ports still assigned to the old+*one,soonlyallowitwhilethey'redown,anddon'tallowthemto+*comebackupuntilthey'reallchangedtothenewone.+*/+dsa_switch_for_each_user_port(other_dp,ds){+structnet_device*slave=other_dp->slave;++if(other_dp!=dp&&(slave->flags&IFF_UP)&&+dsa_port_to_master(other_dp)!=master){+NL_SET_ERR_MSG_MOD(extack,+"Cannot change while old master still has users");+return-EOPNOTSUPP;+}+}++felix_npi_port_deinit(ocelot,ocelot->npi);+felix_npi_port_init(ocelot,felix_cpu_port_for_master(ds,master));++return0;+}+/* Alternatively to using the NPI functionality, that same hardware MAC*connectedinternallytotheenetcorfmanDSAmastercanbeconfiguredto*usethesoftware-definedtag_8021qframeformat.Asfarasthehardwareis
@@ -864,8 +941,17 @@ static int felix_lag_join(struct dsa_switch *ds, int port,structnetdev_lag_upper_info*info){structocelot*ocelot=ds->priv;+interr;-returnocelot_port_lag_join(ocelot,port,lag.dev,info);+err=ocelot_port_lag_join(ocelot,port,lag.dev,info);+if(err)+returnerr;++/* Update the logical LAG port that serves as tag_8021q CPU port */+if(!dsa_is_cpu_port(ds,port))+return0;++returnfelix_port_change_master(ds,port,lag.dev,NULL);}staticintfelix_lag_leave(structdsa_switch*ds,intport,
@@ -875,7 +961,11 @@ static int felix_lag_leave(struct dsa_switch *ds, int port,ocelot_port_lag_leave(ocelot,port,lag.dev);-return0;+/* Update the logical LAG port that serves as tag_8021q CPU port */+if(!dsa_is_cpu_port(ds,port))+return0;++returnfelix_port_change_master(ds,port,lag.dev,NULL);}staticintfelix_lag_change(structdsa_switch*ds,intport)
@@ -1013,6 +1103,27 @@ static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port,felix->info->port_sched_speed_set(ocelot,port,speed);}+staticintfelix_port_enable(structdsa_switch*ds,intport,+structphy_device*phydev)+{+structdsa_port*dp=dsa_to_port(ds,port);+structocelot*ocelot=ds->priv;++if(!dsa_port_is_user(dp))+return0;++if(ocelot->npi>=0){+structnet_device*master=dsa_port_to_master(dp);++if(felix_cpu_port_for_master(ds,master)!=ocelot->npi){+dev_err(ds->dev,"Multiple masters are not allowed\n");+return-EINVAL;+}+}++return0;+}+staticvoidfelix_port_qos_map_init(structocelot*ocelot,intport){inti;
@@ -2054,7 +2054,7 @@ static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)/* The logical port number of a LAG is equal to the lowest numbered physical*portIDpresentinthatLAG.ItmaychangeifthatporteverleavestheLAG.*/-staticintocelot_bond_get_id(structocelot*ocelot,structnet_device*bond)+intocelot_bond_get_id(structocelot*ocelot,structnet_device*bond){intbond_mask=ocelot_get_bond_mask(ocelot,bond);
@@ -2063,6 +2063,7 @@ static int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)return__ffs(bond_mask);}+EXPORT_SYMBOL_GPL(ocelot_bond_get_id);/* Returns the mask of user ports assigned to this DSA tag_8021q CPU port.*NotethatwhenCPUportsareinaLAG,theuserportsareassignedtothe
@@ -1105,6 +1105,7 @@ int ocelot_port_lag_join(struct ocelot *ocelot, int port,voidocelot_port_lag_leave(structocelot*ocelot,intport,structnet_device*bond);voidocelot_port_lag_change(structocelot*ocelot,intport,boollag_tx_active);+intocelot_bond_get_id(structocelot*ocelot,structnet_device*bond);intocelot_devlink_sb_register(structocelot*ocelot);voidocelot_devlink_sb_unregister(structocelot*ocelot);
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-09-02 10:31:57
On Tue, Aug 30, 2022 at 10:59:23PM +0300, Vladimir Oltean wrote:
This series represents the final part of that effort. We have:
- the introduction of new UAPI in the form of IFLA_DSA_MASTER
Call for opinions: when I resend this, should I keep rtnl_link_ops,
or should I do what Marek attempted to do, and make the existing iflink
between a user port and its master writable from user space?
https://lore.kernel.org/netdev/20190824024251.4542-4-marek.behun@nic.cz/
I'm not sure if we have that many more use cases for rtnl_link_ops..
at some point I was thinking we could change the way in which dsa_loop
probes, and allow dynamic creation of such interfaces using RTM_NEWLINK;
but looking closer at that, it's a bit more complicated, since we'd need
to attach dsa_loop user ports to a virtual switch, and probe all ports
at the same time rather than one by one.
On Tue, Aug 30, 2022 at 10:59:23PM +0300, Vladimir Oltean wrote:
quoted
This series represents the final part of that effort. We have:
- the introduction of new UAPI in the form of IFLA_DSA_MASTER
Call for opinions: when I resend this, should I keep rtnl_link_ops,
or should I do what Marek attempted to do, and make the existing iflink
between a user port and its master writable from user space?
https://lore.kernel.org/netdev/20190824024251.4542-4-marek.behun@nic.cz/
I'm not sure if we have that many more use cases for rtnl_link_ops..
It's a bit hard to see one right now, I agree.
at some point I was thinking we could change the way in which dsa_loop
probes, and allow dynamic creation of such interfaces using RTM_NEWLINK;
but looking closer at that, it's a bit more complicated, since we'd need
to attach dsa_loop user ports to a virtual switch, and probe all ports
at the same time rather than one by one.
Yes, not sure the custom netlink operations would be the preferred way
of doing that configuration, maybe module parameters and/or debugfs
might just do?
--
Florian
From: Vladimir Oltean <olteanv@gmail.com> Date: 2022-09-02 18:40:15
On Fri, Sep 02, 2022 at 11:33:31AM -0700, Florian Fainelli wrote:
quoted
at some point I was thinking we could change the way in which dsa_loop
probes, and allow dynamic creation of such interfaces using RTM_NEWLINK;
but looking closer at that, it's a bit more complicated, since we'd need
to attach dsa_loop user ports to a virtual switch, and probe all ports
at the same time rather than one by one.
Yes, not sure the custom netlink operations would be the preferred way of
doing that configuration, maybe module parameters and/or debugfs might just
do?
Yeah, or make dsa_loop OF-based and just insert a device tree overlay,
something of that sort, I'd guess.
So it's likely that we won't be extending the DSA rtnl_link_ops too much
in the future. However, it's also likely that "writable iflink" isn't
going to be very useful for other virtual netdevices except DSA, either.
So the argument goes both ways. And while the writable iflink requires a
new ndo operation, the IFLA_DSA_MASTER can be handled 100% within DSA.
I don't know, I'm just rambling, I'm open to suggestions.
From: Marek Behún <kabel@kernel.org> Date: 2022-09-03 02:48:48
On Fri, 2 Sep 2022 10:31:46 +0000
Vladimir Oltean [off-list ref] wrote:
On Tue, Aug 30, 2022 at 10:59:23PM +0300, Vladimir Oltean wrote:
quoted
This series represents the final part of that effort. We have:
- the introduction of new UAPI in the form of IFLA_DSA_MASTER
Call for opinions: when I resend this, should I keep rtnl_link_ops,
or should I do what Marek attempted to do, and make the existing iflink
between a user port and its master writable from user space?
https://lore.kernel.org/netdev/20190824024251.4542-4-marek.behun@nic.cz/
I'm not sure if we have that many more use cases for rtnl_link_ops..
at some point I was thinking we could change the way in which dsa_loop
probes, and allow dynamic creation of such interfaces using RTM_NEWLINK;
but looking closer at that, it's a bit more complicated, since we'd need
to attach dsa_loop user ports to a virtual switch, and probe all ports
at the same time rather than one by one.
My opinion is that it would be better to add new DSA specific netlink
operations instead of using the existing iflink as I did in the that
patch.
I think that DSA should have it's own IP subcommands. Using the
standard, already existing API, is not sufficient for more complex
configurations/DSA routing settings. Consider DSA where there are
multiple switches and the switches are connected via multiple ports:
+----------+ +---------------+ +---------+
| eth0 <---> sw0p0 sw0p2 <---> sw1p0
| cpu | | | | ....
| eth1 <---> sw0p1 s20p3 <---> sw1p1
+----------+ +---------------+ +---------+
The routing is more complicated in this scenario. The old API is not
sufficient.
Marek
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-09-04 15:41:30
On Sat, Sep 03, 2022 at 04:48:32AM +0200, Marek Behún wrote:
My opinion is that it would be better to add new DSA specific netlink
operations instead of using the existing iflink as I did in the that
patch.
Ok, I'll send out the iproute2 patch today.
I think that DSA should have it's own IP subcommands. Using the
standard, already existing API, is not sufficient for more complex
configurations/DSA routing settings. Consider DSA where there are
multiple switches and the switches are connected via multiple ports:
+----------+ +---------------+ +---------+
| eth0 <---> sw0p0 sw0p2 <---> sw1p0
| cpu | | | | ....
| eth1 <---> sw0p1 s20p3 <---> sw1p1
+----------+ +---------------+ +---------+
The routing is more complicated in this scenario.
This is so problematic that I don't even know where to start.
Does anyone do this? What do they want to achieve? How do they want the
system to behave?
Let's push your example even one step further:
+----------+ +---------------+ +---------------+ +---------+
| eth0 <---> sw0p0 sw0p2 <---> sw1p0 sw1p2 <---> sw2p0
| cpu | | | | | | ....
| eth1 <---> sw0p1 sw0p3 <---> sw1p1 sw1p3 <---> sw2p1
+----------+ +---------------+ +---------------+ +---------+
With our current DT bindings, DSA (cascade) ports would need to contain
links to all DSA ports of indirectly connected switches, because this is
what the dst->rtable expects.
switch@0 {
reg = <0>;
dsa,member = <0 0>;
ethernet-ports {
port@0 {
reg = <0>;
ethernet = <ð0>;
};
port@1 {
reg = <1>;
ethernet = <ð1>;
};
sw0p2: port@2 {
reg = <2>;
link = <&sw1p0>, <&sw2p0>, <&sw2p1>;
};
sw0p3: port@3 {
reg = <3>;
link = <&sw1p1>, <&sw2p0>, <&sw2p1>;
};
};
};
switch@1 {
reg = <1>;
dsa,member = <0 1>;
ethernet-ports {
sw1p0: port@0 {
reg = <0>;
link = <&sw0p2>;
};
sw1p1: port@1 {
reg = <1>;
link = <&sw0p3>;
};
sw1p2: port@2 {
reg = <2>;
link = <&sw2p0>;
};
sw1p3: port@3 {
reg = <3>;
link = <&sw2p1>;
};
};
};
switch@2 {
reg = <2>;
dsa,member = <0 2>;
ethernet-ports {
port@0 {
reg = <0>;
link = <&sw1p2>, <&sw0p2>, <&sw0p3>;
};
port@1 {
reg = <1>;
link = <&sw1p3>, <&sw0p2>, <&sw0p3>;
};
};
};
The old API is not sufficient.
There is no "old API" to speak of, because none of this is exposed.
So, 'insufficient' is an understatement. Furthermore, the rtnl_link_ops
are exposed per *user* port, we still gain zero control of the
dst->rtable.
The main consumer of the dst->rtable is this:
/* Return the local port used to reach an arbitrary switch device */
static inline unsigned int dsa_routing_port(struct dsa_switch *ds, int device)
{
struct dsa_switch_tree *dst = ds->dst;
struct dsa_link *dl;
list_for_each_entry(dl, &dst->rtable, list)
if (dl->dp->ds == ds && dl->link_dp->ds->index == device)
return dl->dp->index;
return ds->num_ports;
}
Notice the singular *the* local port. So it would currently return the
local cascade port from the first dsa_link added to the rtable (in turn,
the first port which has a 'link' OF node description to a cascade port
of @device). If there are any further dsa_links between a cascade port
of this switch and a cascade port of that switch, they are ignored
(which is a good thing in terms of compatibility between old kernels and
new device trees, but still raises questions).
For each of the functions in the call graph below, we need to determine
exactly what we need to make behave differently (consider a potential
second, third, fourth dsa_link, and how to expose this structure):
dsa_port_host_address_match
|
| dsa_port_host_vlan_match
| |
v v
dsa_switch_is_upstream_of
| |
| |
| mv88e6xxx_lag_sync_map |
v | |
dsa_is_upstream_port | |
| | |
mv88e6xxx_port_vlan | | |
| | | |
v | | |
dsa_switch_upstream_port | | |
| | | |
| | | |
plenty of drivers | | | |
| | | | |
v v v | |
dsa_upstream_port | |
| | |
v v |
dsa_towards_port |
| |
| |
v v
dsa_routing_port
From: Christian Marangi <ansuelsmth@gmail.com> Date: 2022-09-02 18:44:51
On Tue, Aug 30, 2022 at 10:59:23PM +0300, Vladimir Oltean wrote:
Those who have been following part 1:
https://patchwork.kernel.org/project/netdevbpf/cover/20220511095020.562461-1-vladimir.oltean@nxp.com/
part 2:
https://patchwork.kernel.org/project/netdevbpf/cover/20220521213743.2735445-1-vladimir.oltean@nxp.com/
and part 3:
https://patchwork.kernel.org/project/netdevbpf/cover/20220819174820.3585002-1-vladimir.oltean@nxp.com/
will know that I am trying to enable the second internal port pair from
the NXP LS1028A Felix switch for DSA-tagged traffic via "ocelot-8021q".
This series represents the final part of that effort. We have:
- the introduction of new UAPI in the form of IFLA_DSA_MASTER
- preparation for LAG DSA masters in terms of suppressing some
operations for masters in the DSA core that simply don't make sense
when those masters are a bonding/team interface
- handling all the net device events that occur between DSA and a
LAG DSA master, including migration to a different DSA master when the
current master joins a LAG, or the LAG gets destroyed
- updating documentation
- adding an implementation for NXP LS1028A, where things are insanely
complicated due to hardware limitations. We have 2 tagging protocols:
* the native "ocelot" protocol (NPI port mode). This does not support
CPU ports in a LAG, and supports a single DSA master. The DSA master
can be changed between eno2 (2.5G) and eno3 (1G), but all ports must
be down during the changing process, and user ports assigned to the
old DSA master will refuse to come up if the user requests that
during a "transient" state.
* the "ocelot-8021q" software-defined protocol, where the Ethernet
ports connected to the CPU are not actually "god mode" ports as far
as the hardware is concerned. So here, static assignment between
user and CPU ports is possible by editing the PGID_SRC masks for
the port-based forwarding matrix, and "CPU ports in a LAG" simply
means "a LAG like any other".
The series was regression-tested on LS1028A using the local_termination.sh
kselftest, in most of the possible operating modes and tagging protocols.
I have not done a detailed performance evaluation yet, but using LAG, is
possible to exceed the termination bandwidth of a single CPU port in an
iperf3 test with multiple senders and multiple receivers.
There was a previous RFC posted, which contains most of these changes,
however it's so old by now that it's unlikely anyone of the reviewers
remembers it in detail. I've applied most of the feedback requested by
Florian and Ansuel there.
https://lore.kernel.org/netdev/20220523104256.3556016-1-olteanv@gmail.com/
Hi,
I would love to test this but for me it's a bit problematic to use a
net-next kernel. I wonder if it's possible to backport the 4 part to
older kernel or other prereq are needed. (I know backporting the 4 part
will be crazy but it's something that has to be done anyway to actually
use this on OpenWrt where we currently use 5.10 and 5.15)
Would be good to know if the 4 part require other changes to dsa core to
make a LAG implementation working. (talking for 5.15 since backporting
this to 5.10 is a nono...)
Vladimir Oltean (9):
net: introduce iterators over synced hw addresses
net: dsa: introduce dsa_port_get_master()
net: dsa: allow the DSA master to be seen and changed through
rtnetlink
net: dsa: don't keep track of admin/oper state on LAG DSA masters
net: dsa: suppress appending ethtool stats to LAG DSA masters
net: dsa: suppress device links to LAG DSA masters
net: dsa: allow masters to join a LAG
docs: net: dsa: update information about multiple CPU ports
net: dsa: felix: add support for changing DSA master
.../networking/dsa/configuration.rst | 84 +++++
Documentation/networking/dsa/dsa.rst | 38 ++-
drivers/net/dsa/bcm_sf2.c | 4 +-
drivers/net/dsa/bcm_sf2_cfp.c | 4 +-
drivers/net/dsa/lan9303-core.c | 4 +-
drivers/net/dsa/ocelot/felix.c | 117 ++++++-
drivers/net/dsa/ocelot/felix.h | 3 +
.../net/ethernet/mediatek/mtk_ppe_offload.c | 2 +-
drivers/net/ethernet/mscc/ocelot.c | 3 +-
include/linux/netdevice.h | 6 +
include/net/dsa.h | 19 ++
include/soc/mscc/ocelot.h | 1 +
include/uapi/linux/if_link.h | 10 +
net/dsa/Makefile | 10 +-
net/dsa/dsa.c | 9 +
net/dsa/dsa2.c | 34 ++-
net/dsa/dsa_priv.h | 17 +-
net/dsa/master.c | 82 ++++-
net/dsa/netlink.c | 62 ++++
net/dsa/port.c | 159 +++++++++-
net/dsa/slave.c | 288 +++++++++++++++++-
net/dsa/switch.c | 22 +-
net/dsa/tag_8021q.c | 4 +-
23 files changed, 924 insertions(+), 58 deletions(-)
create mode 100644 net/dsa/netlink.c
--
2.34.1
From: Marek Behún <kabel@kernel.org> Date: 2022-09-03 02:50:20
On Fri, 2 Sep 2022 20:44:37 +0200
Christian Marangi [off-list ref] wrote:
On Tue, Aug 30, 2022 at 10:59:23PM +0300, Vladimir Oltean wrote:
quoted
Those who have been following part 1:
https://patchwork.kernel.org/project/netdevbpf/cover/20220511095020.562461-1-vladimir.oltean@nxp.com/
part 2:
https://patchwork.kernel.org/project/netdevbpf/cover/20220521213743.2735445-1-vladimir.oltean@nxp.com/
and part 3:
https://patchwork.kernel.org/project/netdevbpf/cover/20220819174820.3585002-1-vladimir.oltean@nxp.com/
will know that I am trying to enable the second internal port pair from
the NXP LS1028A Felix switch for DSA-tagged traffic via "ocelot-8021q".
This series represents the final part of that effort. We have:
- the introduction of new UAPI in the form of IFLA_DSA_MASTER
- preparation for LAG DSA masters in terms of suppressing some
operations for masters in the DSA core that simply don't make sense
when those masters are a bonding/team interface
- handling all the net device events that occur between DSA and a
LAG DSA master, including migration to a different DSA master when the
current master joins a LAG, or the LAG gets destroyed
- updating documentation
- adding an implementation for NXP LS1028A, where things are insanely
complicated due to hardware limitations. We have 2 tagging protocols:
* the native "ocelot" protocol (NPI port mode). This does not support
CPU ports in a LAG, and supports a single DSA master. The DSA master
can be changed between eno2 (2.5G) and eno3 (1G), but all ports must
be down during the changing process, and user ports assigned to the
old DSA master will refuse to come up if the user requests that
during a "transient" state.
* the "ocelot-8021q" software-defined protocol, where the Ethernet
ports connected to the CPU are not actually "god mode" ports as far
as the hardware is concerned. So here, static assignment between
user and CPU ports is possible by editing the PGID_SRC masks for
the port-based forwarding matrix, and "CPU ports in a LAG" simply
means "a LAG like any other".
The series was regression-tested on LS1028A using the local_termination.sh
kselftest, in most of the possible operating modes and tagging protocols.
I have not done a detailed performance evaluation yet, but using LAG, is
possible to exceed the termination bandwidth of a single CPU port in an
iperf3 test with multiple senders and multiple receivers.
There was a previous RFC posted, which contains most of these changes,
however it's so old by now that it's unlikely anyone of the reviewers
remembers it in detail. I've applied most of the feedback requested by
Florian and Ansuel there.
https://lore.kernel.org/netdev/20220523104256.3556016-1-olteanv@gmail.com/
Hi,
I would love to test this but for me it's a bit problematic to use a
net-next kernel. I wonder if it's possible to backport the 4 part to
older kernel or other prereq are needed. (I know backporting the 4 part
will be crazy but it's something that has to be done anyway to actually
use this on OpenWrt where we currently use 5.10 and 5.15)
Would be good to know if the 4 part require other changes to dsa core to
make a LAG implementation working. (talking for 5.15 since backporting
this to 5.10 is a nono...)
Just use the newest kernel. Trust me, backporting new DSA changes to
5.15 is painful. And to 5.10 and earlier it is a literal hell.
:) Marek
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-09-04 19:34:31
On Fri, Sep 02, 2022 at 08:44:37PM +0200, Christian Marangi wrote:
Hi,
I would love to test this but for me it's a bit problematic to use a
net-next kernel. I wonder if it's possible to backport the 4 part to
older kernel or other prereq are needed. (I know backporting the 4 part
will be crazy but it's something that has to be done anyway to actually
use this on OpenWrt where we currently use 5.10 and 5.15)
Would be good to know if the 4 part require other changes to dsa core to
make a LAG implementation working. (talking for 5.15 since backporting
this to 5.10 is a nono...)
For testing, iproute2 patch should be coming up soon here:
https://lore.kernel.org/netdev/20220904190025.813574-1-vladimir.oltean@nxp.com/
I tried to backport something on the current linux-stable/linux-5.15.y.
https://github.com/vladimiroltean/linux/tree/dsa-5.15.y
Consider it a work in progress. It compiles and boots on NXP LS1028A,
but I can't guarantee anything beyond that. Furthermore, I've only
backported the merged patches, not the patch set discussed here proper.
I think it would be nice if we had a collaborative tree with DSA
backports for 5.15, because here I just tried to backport the DSA core
rather than all driver changes (since I would be unable to test those).
For transparency, here is the commit list I used to produce the backport (top-most is most recent):
$ cat stable-commits.txt
5dc760d12082 net: dsa: use dsa_tree_for_each_cpu_port in dsa_tree_{setup,teardown}_master
f41ec1fd1c20 net: dsa: all DSA masters must be down when changing the tagging protocol
7136097e1199 net: dsa: only bring down user ports assigned to a given DSA master
4f03dcc6b9a0 net: dsa: existing DSA masters cannot join upper interfaces
920a33cd7231 net: bridge: move DSA master bridging restriction to DSA
0498277ee17b net: dsa: don't stop at NOTIFY_OK when calling ds->ops->port_prechangeupper
4c3f80d22b2e net: dsa: walk through all changeupper notifier functions
be6ff9665d64 net: dsa: don't emit targeted cross-chip notifiers for MTU change
4715029fa7e9 net: dsa: drop dsa_slave_priv from dsa_slave_change_mtu
cf1c39d3b3a5 net: dsa: avoid one dsa_to_port() in dsa_slave_change_mtu
b2033a05a719 net: dsa: use dsa_tree_for_each_user_port in dsa_slave_change_mtu
726816a129cb net: dsa: make cross-chip notifiers more efficient for host events
8e9e678e4758 net: dsa: move reset of VLAN filtering to dsa_port_switchdev_unsync_attrs
762c2998c962 Revert "net: dsa: setup master before ports"
8e6598a7b0fa net: dsa: Pass VLAN MSTI migration notifications to driver
332afc4c8c0d net: dsa: Validate hardware support for MST
f54fd0e16306 net: bridge: mst: Add helper to query a port's MST state
48d57b2e5f43 net: bridge: mst: Add helper to check if MST is enabled
cceac97afa09 net: bridge: mst: Add helper to map an MSTI to a VID set
7ae9147f4312 net: bridge: mst: Notify switchdev drivers of MST state changes
6284c723d9b9 net: bridge: mst: Notify switchdev drivers of VLAN MSTI migrations
87c167bb94ee net: bridge: mst: Notify switchdev drivers of MST mode changes
122c29486e1f net: bridge: mst: Support setting and reporting MST port states
8c678d60562f net: bridge: mst: Allow changing a VLAN's MSTI
ec7328b59176 net: bridge: mst: Multiple Spanning Tree (MST) mode
0832cd9f1f02 net: dsa: warn if port lists aren't empty in dsa_port_teardown
afb3cc1a397d net: dsa: unlock the rtnl_mutex when dsa_master_setup() fails
7569459a52c9 net: dsa: manage flooding on the CPU ports
499aa9e1b332 net: dsa: install the primary unicast MAC address as standalone port host FDB
5e8a1e03aa4d net: dsa: install secondary unicast and multicast addresses as host FDB/MDB
68d6d71eafd1 net: dsa: rename the host FDB and MDB methods to contain the "bridge" namespace
35aae5ab9121 net: dsa: remove workarounds for changing master promisc/allmulti only while up
06b9cce42634 net: dsa: pass extack to .port_bridge_join driver methods
c26933639b54 net: dsa: request drivers to perform FDB isolation
b6362bdf750b net: dsa: tag_8021q: rename dsa_8021q_bridge_tx_fwd_offload_vid
04b67e18ce5b net: dsa: tag_8021q: merge RX and TX VLANs
08f44db3abe6 net: dsa: felix: delete workarounds present due to SVL tag_8021q bridging
d27656d02d85 docs: net: dsa: sja1105: document limitations of tc-flower rule VLAN awareness
d7f9787a763f net: dsa: tag_8021q: add support for imprecise RX based on the VBID
91495f21fcec net: dsa: tag_8021q: replace the SVL bridging with VLAN-unaware IVL bridging
961d8b699070 net: dsa: felix: support FDB entries on offloaded LAG interfaces
e212fa7c5418 net: dsa: support FDB events on offloaded LAG interfaces
93c798230af5 net: dsa: call SWITCHDEV_FDB_OFFLOADED for the orig_dev
e35f12e993d4 net: dsa: remove "ds" and "port" from struct dsa_switchdev_event_work
ec638740fce9 net: switchdev: remove lag_mod_cb from switchdev_handle_fdb_event_to_device
dedd6a009f41 net: dsa: create a dsa_lag structure
b99dbdf00bc1 net: dsa: mv88e6xxx: use dsa_switch_for_each_port in mv88e6xxx_lag_sync_masks
3d4a0a2a46ab net: dsa: make LAG IDs one-based
066ce9779c7a net: dsa: qca8k: rename references to "lag" as "lag_dev"
e23eba722861 net: dsa: mv88e6xxx: rename references to "lag" as "lag_dev"
46a76724e4c9 net: dsa: rename references to "lag" as "lag_dev"
b9e8b58fd2cb net: dsa: Include BR_PORT_LOCKED in the list of synced brport flags
a21d9a670d81 net: bridge: Add support for bridge port in locked mode
acd8df5880d7 net: switchdev: avoid infinite recursion from LAG to bridge with port object handler
342b6419193c net: dsa: fix panic when removing unoffloaded port from bridge
8940e6b669ca net: dsa: avoid call to __dev_set_promiscuity() while rtnl_mutex isn't held
ba43b547515e net: lan966x: remove guards against !BRIDGE_VLAN_INFO_BRENTRY
e42bd4ed09aa net: mscc: ocelot: keep traps in a list
85ea0daabe5a net: mscc: ocelot: avoid overlap in VCAP IS2 between PTP and MRP traps
b9bace6e534d net: mscc: ocelot: use a single VCAP filter for all MRP traps
36fac35b2907 net: mscc: ocelot: delete OCELOT_MRP_CPUQ
c518afec2883 net: mscc: ocelot: consolidate cookie allocation for private VCAP rules
e3c02b7c655c net: mscc: ocelot: use a consistent cookie for MRP traps
164f861bd40c net: dsa: offload bridge port VLANs on foreign interfaces
134ef2388e7f net: dsa: add explicit support for host bridge VLANs
c4076cdd21f8 net: switchdev: introduce switchdev_handle_port_obj_{add,del} for foreign interfaces
7b465f4cf39e net: switchdev: rename switchdev_lower_dev_find to switchdev_lower_dev_find_rcu
b28d580e2939 net: bridge: switchdev: replay all VLAN groups
263029ae3172 net: bridge: make nbp_switchdev_unsync_objs() follow reverse order of sync()
8d23a54f5bee net: bridge: switchdev: differentiate new VLANs from changed ones
27c5f74c7ba7 net: bridge: vlan: notify switchdev only when something changed
cab2cd770051 net: bridge: vlan: make __vlan_add_flags react only to PVID and UNTAGGED
3116ad0696dd net: bridge: vlan: don't notify to switchdev master VLANs without BRENTRY flag
b2bc58d41fde net: bridge: vlan: check early for lack of BRENTRY flag in br_vlan_add_existing
ef5764057540 net: mscc: ocelot: fix use-after-free in ocelot_vlan_del()
5454f5c28eca net: bridge: vlan: check for errors from __vlan_del in __vlan_flush
867b1db874c9 net: lan966x: Fix when CONFIG_IPV6 is not set
1da52b0e4724 net: lan966x: Fix when CONFIG_PTP_1588_CLOCK is compiled as module
59085208e4a2 net: mscc: ocelot: fix all IP traffic getting trapped to CPU with PTP over IP
47aeea0d57e8 net: lan966x: Implement the callback SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED
cddbec19466a net: dsa: qca8k: add tracking state of master port
e83d56537859 net: dsa: replay master state events in dsa_tree_{setup,teardown}_master
295ab96f478d net: dsa: provide switch operations for tracking the master state
a1ff94c2973c net: dsa: stop updating master MTU from master.c
77eecf25bd9d net: lan966x: Update extraction/injection for timestamping
735fec995b21 net: lan966x: Implement SIOCSHWTSTAMP and SIOCGHWTSTAMP
d096459494a8 net: lan966x: Add support for ptp clocks
108dc8741c20 net: dsa: Avoid cross-chip syncing of VLAN filtering
381a730182f1 net: dsa: Move VLAN filtering syncing out of dsa_switch_bridge_leave
5cad43a52ee3 net: dsa: felix: add port fast age support
1b26d364e4e9 net: dsa: warn about dsa_port and dsa_switch bit fields being non atomic
63cfc65753d6 net: dsa: don't enumerate dsa_switch and dsa_port bit fields using commas
11fd667dac31 net: dsa: setup master before ports
1e3f407f3cac net: dsa: first set up shared ports, then non-shared ports
c146f9bc195a net: dsa: hold rtnl_mutex when calling dsa_master_{setup,teardown}
a68dc7b938fb net: dsa: remove cross-chip support for HSR
cad69019f2f8 net: dsa: remove cross-chip support for MRP
4b026e82893b net: dsa: combine two holes in struct dsa_switch_tree
b035c88c6a30 net: dsa: move dsa_switch_tree :: ports and lags to first cache line
258030acc93b net: dsa: make dsa_switch :: num_ports an unsigned int
7787ff776398 net: dsa: merge all bools of struct dsa_switch into a single u32
0625125877da net: dsa: move dsa_port :: type near dsa_port :: index
bde82f389af1 net: dsa: merge all bools of struct dsa_port into a single u8
b08db33dabd1 net: dsa: move dsa_port :: stp_state near dsa_port :: mac
7aacb894b1ad net: lan966x: Extend switchdev with mdb support
11b0a27772f5 net: lan966x: Add PGID_GP_START and PGID_GP_END
fc0c3fe7486f net: lan966x: Add function lan966x_mac_ip_learn()
0c94d657d2a4 net: lan966x: Fix the vlan used by host ports
2e49761e4fd1 net: lan966x: Add support for multiple bridge flags
811ba2771182 net: lan966x: Extend switchdev with fdb support
e14f72398df4 net: lan966x: Extend switchdev bridge flags
6d2c186afa5d net: lan966x: Add vlan support.
cf2f60897e92 net: lan966x: Add support to offload the forwarding.
571bb516a869 net: lan966x: Remove .ndo_change_rx_flags
25ee9561ec62 net: lan966x: More MAC table functionality
5ccd66e01cbe net: lan966x: add support for interrupts from analyzer
ef14049f4db9 net: lan966x: Add registers that are used for switch and vlan functionality
7f2973149c22 net: dsa: make tagging protocols connect to individual switches from a tree
e2f01bfe1406 net: dsa: tag_sja1105: fix zeroization of ds->priv on tag proto disconnect
b26980ab2a97 net: lan966x: Fix the configuration of the pcs
950a419d9de1 net: dsa: tag_sja1105: split sja1105_tagger_data into private and public sections
fcbf979a5b4b Revert "net: dsa: move sja1110_process_meta_tstamp inside the tagging protocol driver"
c79e84866d2a net: dsa: tag_sja1105: convert to tagger-owned data
22ee9f8e4011 net: dsa: sja1105: move ts_id from sja1105_tagger_data
bfcf14252220 net: dsa: sja1105: make dp->priv point directly to sja1105_tagger_data
6f6770ab1ce2 net: dsa: sja1105: remove hwts_tx_en from tagger data
d38049bbe760 net: dsa: sja1105: bring deferred xmit implementation in line with ocelot-8021q
a3d74295d790 net: dsa: sja1105: let deferred packets time out when sent to ports going down
35d976802124 net: dsa: tag_ocelot: convert to tagger-owned data
dc452a471dba net: dsa: introduce tagger-owned storage for private and shared data
857fdd74fb38 net: dsa: eliminate dsa_switch_ops :: port_bridge_tx_fwd_{,un}offload
b079922ba2ac net: dsa: add a "tx_fwd_offload" argument to ->port_bridge_join
d3eed0e57d5d net: dsa: keep the bridge_dev and bridge_num as part of the same structure
6a43cba30340 net: dsa: export bridging offload helpers to drivers
936db8a2dba2 net: dsa: rename dsa_port_offloads_bridge to dsa_port_offloads_bridge_dev
41fb0cf1bced net: dsa: hide dp->bridge_dev and dp->bridge_num in drivers behind helpers
36cbf39b5690 net: dsa: hide dp->bridge_dev and dp->bridge_num in the core behind helpers
65144067d360 net: dsa: mv88e6xxx: compute port vlan membership based on dp->bridge_dev comparison
0493fa7927af net: dsa: mv88e6xxx: iterate using dsa_switch_for_each_user_port in mv88e6xxx_port_check_hw_vlan
872bb81dfbc3 net: dsa: mt7530: iterate using dsa_switch_for_each_user_port in bridging ops
947c8746e2c3 net: dsa: assign a bridge number even without TX forwarding offload
3f9bb0301d50 net: dsa: make dp->bridge_num one-based
bb14bfc7eb92 net: lan966x: fix a IS_ERR() vs NULL check in lan966x_create_targets()
cc9cf69eea48 net: lan966x: Fix builds for lan966x driver
a290cf692779 net: lan966x: Fix duplicate check in frame extraction
12c2d0a5b8e2 net: lan966x: add ethtool configuration and statistics
e18aba8941b4 net: lan966x: add mactable support
d28d6d2e37d1 net: lan966x: add port module support
db8bcaad5393 net: lan966x: add the basic lan966x driver
ef136837aaf6 net: dsa: rtl8365mb: set RGMII RX delay in steps of 0.3 ns
b014861d96a6 net: dsa: realtek-smi: don't log an error on EPROBE_DEFER
1e89ad864d03 net: dsa: realtek-smi: fix indirect reg access for ports>3
b3612ccdf284 net: dsa: microchip: implement multi-bridge support
96ca08c05838 net: mscc: ocelot: set up traps for PTP packets
ec15baec3272 net: ptp: add a definition for the UDP port for IEEE 1588 general messages
95706be13b9f net: mscc: ocelot: create a function that replaces an existing VCAP filter
8abe19703825 net: dsa: felix: enable cut-through forwarding between ports by default
a8bd9fa5b527 net: ocelot: remove "bridge" argument from ocelot_get_bridge_fwd_mask
4636440f913b net: dsa: qca8k: Fix spelling mistake "Mismateched" -> "Mismatched"
0898ca67b86e net: dsa: qca8k: fix warning in LAG feature
def975307c01 net: dsa: qca8k: add LAG support
2c1bdbc7e756 net: dsa: qca8k: add support for mirror mode
ba8f870dfa63 net: dsa: qca8k: add support for mdb_add/del
6a3bdc5209f4 net: dsa: qca8k: add set_ageing_time support
4592538bfb0d net: dsa: qca8k: add support for port fast aging
c126f118b330 net: dsa: qca8k: add additional MIB counter and make it dynamic
8b5f3f29a81a net: dsa: qca8k: initial conversion to regmap helper
36b8af12f424 net: dsa: qca8k: move regmap init in probe and set it mandatory
994c28b6f971 net: dsa: qca8k: remove extra mutex_init in qca8k_setup
90ae68bfc2ff net: dsa: qca8k: convert to GENMASK/FIELD_PREP/FIELD_GET
b9133f3ef5a2 net: dsa: qca8k: remove redundant check in parse_port_config
65258b9d8cde net: dsa: qca8k: fix MTU calculation
3b00a07c2443 net: dsa: qca8k: fix internal delay applied to the wrong PAD config
a7e13edf37be net: dsa: felix: restrict psfp rules on ingress port
76c13ede7120 net: dsa: felix: use vcap policer to set flow meter for psfp
77043c37096d net: mscc: ocelot: use index to set vcap policer
23ae3a787771 net: dsa: felix: add stream gate settings for psfp
7d4b564d6add net: dsa: felix: support psfp filter on vsc9959
23e2c506ad6c net: mscc: ocelot: add gate and police action offload to PSFP
5b1918a54a91 net: mscc: ocelot: set vcap IS2 chain to goto PSFP chain
0568c3bf3f34 net: mscc: ocelot: add MAC table stream learn and lookup operations
02d6fdecb9c3 regmap: allow to define reg_update_bits for no bus configuration
5f15d392dcb4 net: dsa: qca8k: make sure PAD0 MAC06 exchange is disabled
ae0393500e3b net: bridge: switchdev: fix shim definition for br_switchdev_mdb_notify
326b212e9cd6 net: bridge: switchdev: consistent function naming
9776457c784f net: bridge: mdb: move all switchdev logic to br_switchdev.c
9ae9ff994b0e net: bridge: split out the switchdev portion of br_mdb_notify
4a6849e46173 net: bridge: move br_vlan_replay to br_switchdev.c
c5f6e5ebc2af net: bridge: provide shim definition for br_vlan_flags
716a30a97a52 net: switchdev: merge switchdev_handle_fdb_{add,del}_to_device
fab9eca88410 net: bridge: create a common function for populating switchdev FDB entries
5cda5272a460 net: bridge: move br_fdb_replay inside br_switchdev.c
9574fb558044 net: bridge: reduce indentation level in fdb_create
f6814fdcfe1b net: bridge: rename br_fdb_insert to br_fdb_add_local
4731b6d6b257 net: bridge: rename fdb_insert to fdb_add_local
5f94a5e276ae net: bridge: remove fdb_insert forward declaration
4682048af0c8 net: bridge: remove fdb_notify forward declaration
425d19cedef8 net: dsa: stop calling dev_hold in dsa_slave_fdb_event
d7d0d423dbaa net: dsa: flush switchdev workqueue when leaving the bridge
0faf890fc519 net: dsa: drop rtnl_lock from dsa_slave_switchdev_event_work
338a3a4745aa net: dsa: introduce locking for the address lists on CPU and DSA ports
cf231b436f7c net: dsa: lantiq_gswip: serialize access to the PCE registers
f7eb4a1c0864 net: dsa: b53: serialize access to the ARL table
edc90d15850c selftests: net: dsa: add a stress test for unlocked FDB operations
016748961ba5 selftests: lib: forwarding: allow tests to not require mz and jq
f239934cffe5 net: dsa: b53: serialize access to the ARL table
f2c4bdf62d76 net: mscc: ocelot: serialize access to the MAC table
1681ae1691ef net: dsa: sja1105: serialize access to the dynamic config interface
643979cf5ec4 net: dsa: sja1105: wait for dynamic config command completion on writes too
992e5cc7be8e net: dsa: tag_8021q: make dsa_8021q_{rx,tx}_vid take dp as argument
5068887a4fbe net: dsa: tag_sja1105: do not open-code dsa_switch_for_each_port
fac6abd5f132 net: dsa: convert cross-chip notifiers to iterate using dp
57d77986e742 net: dsa: remove gratuitous use of dsa_is_{user,dsa,cpu}_port
65c563a67755 net: dsa: do not open-code dsa_switch_for_each_port
d0004a020bb5 net: dsa: remove the "dsa_to_port in a loop" antipattern from the core
82b318983c51 net: dsa: introduce helpers for iterating through ports using dp
d4004422f6f9 net: mscc: ocelot: track the port pvid using a pointer
bfbab3104413 net: mscc: ocelot: add the local station MAC addresses in VID 0
0da1a1c48911 net: mscc: ocelot: allow a config where all bridge VLANs are egress-untagged
90e0aa8d108d net: mscc: ocelot: convert the VLAN masks to a list
62a22bcbd30e net: mscc: ocelot: add a type definition for REW_TAG_CFG_TAG_CFG
040e926f5813 net: dsa: qca8k: tidy for loop in setup and add cpu port check
9ca482a246f0 net: dsa: sja1105: parse {rx, tx}-internal-delay-ps properties for RGMII delays
4af2950c50c8 net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC
1521d5adfc2b net: dsa: tag_rtl8_4: add realtek 8 byte protocol 4 tag
9cb8edda2157 net: dsa: move NET_DSA_TAG_RTL4_A to right place in Kconfig/Makefile
7bbbbfaa7a1b ether: add EtherType for proprietary Realtek protocols
fd0bb28c547f net: dsa: qca8k: move port config to dedicated struct
cef08115846e net: dsa: qca8k: set internal delay also for sgmii
f477d1c8bdbe net: dsa: qca8k: add support for QCA8328
ed7988d77fbf dt-bindings: net: dsa: qca8k: document support for qca8328
362bb238d8bf net: dsa: qca8k: add support for pws config reg
924087c5c3d4 dt-bindings: net: dsa: qca8k: Document qca,led-open-drain binding
bbc4799e8bb6 net: dsa: qca8k: add explicit SGMII PLL enable
13ad5ccc093f dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll
5654ec78dd7e net: dsa: qca8k: rework rgmii delay logic and scan for cpu port 6
3fcf734aa482 net: dsa: qca8k: add support for cpu port 6
731d613338ec dt-bindings: net: dsa: qca8k: Document support for CPU port 6
6c43809bf1be net: dsa: qca8k: add support for sgmii falling edge
fdbf35df9c09 dt-bindings: net: dsa: qca8k: Add SGMII clock phase properties
d8b6f5bae6d3 dsa: qca8k: add mac_power_sel support
39e222bfd7f3 net: dsa: unregister cross-chip notifier after ds->ops->teardown
339e75f6b9a0 net: dsa: rtl8366rb: remove unneeded semicolon
e674cfd08537 net: dsa: rtl8366rb: Support setting STP state
1fbd19e10b73 net: dsa: rtl8366rb: Support fast aging
56d8bb71a811 net: dsa: rtl8366rb: Support disabling learning
5ca721c54d86 net: dsa: tag_ocelot: set the classified VLAN during xmit
e8c0722927e8 net: mscc: ocelot: write full VLAN TCI in the injection header
de5bbb6f7e4c net: mscc: ocelot: support egress VLAN rewriting via VCAP ES0
55b115c7ecd9 net: dsa: rtl8366rb: Use core filtering tracking
d310b14ae748 net: dsa: rtl8366: Drop and depromote pointless prints
a4eff910ec63 net: dsa: rtl8366rb: Rewrite weird VLAN filering enablement
7776e33c68ae net: dsa: rtl8366: Drop custom VLAN set-up
d5a680295be2 net: dsa: rtl8366rb: Support bridge offloading
bd936bd53b2d net: dsa: Move devlink registration to be last devlink command
6d709cadfde6 net: dsa: move sja1110_process_meta_tstamp inside the tagging protocol driver
68a81bb2eebd net: dsa: sja1105: remove sp->dp
db4278c55fa5 devlink: Make devlink_register to be void
4dcd183fbd67 net: wwan: iosm: devlink registration
There are 2 conflicts expected during merging this patch set due to net
<-> net-next overlaps at the time. One is in include/linux/dsa/sja1105.h
and the other is in net/dsa/dsa2.c. See the resolutions in my git tree
and make sure to enable git rerere so that you don't have to redo them
every time you recreate the branch.
For sorting a list of commits chronologically, I have this:
$ cat ~/bin/git-sort-commit-list
#!/bin/bash
set -e -u -o pipefail
error() {
local lineno="$1"
local code="${2:-1}"
echo "Error on line ${lineno}; status ${code}."
exit "${code}"
}
trap 'error ${LINENO}' ERR
usage() {
echo "Usage:"
echo "$0 --commit-file <file> --oldest-commit <ref> --newest-commit <ref>"
exit
}
argc=$#
argv=( "$@" )
if [ $argc -lt 6 ]; then
usage
fi
cmd="cat"
i=0
while [ $i -lt $argc ]; do
key="${argv[$i]}"
i=$((i + 1))
case "$key" in
-c|--commit-file)
file="${argv[$i]}"
i=$((i + 1))
;;
-n|--newest-commit)
newest="${argv[$i]}"
i=$((i + 1))
;;
-o|--oldest-commit)
oldest="${argv[$i]}"
i=$((i + 1))
;;
*)
usage
;;
esac
done
for rev in $(git rev-list "$newest" ^"$oldest"); do
match="$(grep $(echo ${rev} | head -c 12) ${file} | uniq || :)"
if [ -n "${match}" ]; then
echo ${match}
fi
done
The other script is for the backporting itself:
[tigrisor@skbuf /opt/linux] $ cat ~/bin/git-backport
#!/bin/bash
set -e -u -o pipefail
error() {
local lineno="$1"
local code="${2:-1}"
echo "Error on line ${lineno}; status ${code}."
exit "${code}"
}
trap 'error ${LINENO}' ERR
usage() {
echo "Usage:"
echo "$0 --commit-file <file> --base-branch <ref> --branch-name <string> [--reverse]"
exit
}
argc=$#
argv=( "$@" )
if [ $argc -lt 6 ]; then
usage
fi
cmd="cat"
i=0
while [ $i -lt $argc ]; do
key="${argv[$i]}"
i=$((i + 1))
case "$key" in
-c|--commit-file)
file="${argv[$i]}"
i=$((i + 1))
;;
-b|--branch-name)
branch_name="${argv[$i]}"
i=$((i + 1))
;;
-B|--base-branch)
base_branch="${argv[$i]}"
i=$((i + 1))
;;
-r|--reverse)
cmd="tac"
i=$((i + 1))
;;
*)
usage
;;
esac
done
git checkout -B "${branch_name}"
git reset --hard "${base_branch}"
GIT_SEQUENCE_EDITOR="${cmd} ${file} | awk '{ print \"pick \" \$0; }' >" \
git rebase -i --rerere-autoupdate "${base_branch}"
I run it using:
$ git-backport --commit-file stable-commits.txt --base-branch linux-5.15.y --branch-name dsa-5.15.y --reverse
You can add commits to the commit list pretty much anywhere, and run the sorting script afterwards:
$ git sort-commit-list --commit-file stable-commits.txt --oldest-commit v5.15 --newest-commit 5dc760d12082 | tee stable-commits-sorted.txt
You'll probably need to add more, and rebase onto a different base branch for OpenWRT. Nonetheless, it should be a valid start.
Have fun and let me know if you have something useful to share back!
From: Colin Foster <colin.foster@in-advantage.com> Date: 2022-09-06 16:35:34
On Sun, Sep 04, 2022 at 07:34:14PM +0000, Vladimir Oltean wrote:
On Fri, Sep 02, 2022 at 08:44:37PM +0200, Christian Marangi wrote:
For transparency, here is the commit list I used to produce the backport (top-most is most recent):
Tangentially related: how did you come up with this list?
I can only assume this is a manual process based on intricate knowledge
of net / DSA as a whole. I just want to make sure there isn't a "git
backport net/dsa origin/master v5.10" sort of thing ;-)
$ cat stable-commits.txt
5dc760d12082 net: dsa: use dsa_tree_for_each_cpu_port in dsa_tree_{setup,teardown}_master
f41ec1fd1c20 net: dsa: all DSA masters must be down when changing the tagging protocol
7136097e1199 net: dsa: only bring down user ports assigned to a given DSA master
4f03dcc6b9a0 net: dsa: existing DSA masters cannot join upper interfaces
920a33cd7231 net: bridge: move DSA master bridging restriction to DSA
0498277ee17b net: dsa: don't stop at NOTIFY_OK when calling ds->ops->port_prechangeupper
4c3f80d22b2e net: dsa: walk through all changeupper notifier functions
be6ff9665d64 net: dsa: don't emit targeted cross-chip notifiers for MTU change
4715029fa7e9 net: dsa: drop dsa_slave_priv from dsa_slave_change_mtu
cf1c39d3b3a5 net: dsa: avoid one dsa_to_port() in dsa_slave_change_mtu
b2033a05a719 net: dsa: use dsa_tree_for_each_user_port in dsa_slave_change_mtu
726816a129cb net: dsa: make cross-chip notifiers more efficient for host events
8e9e678e4758 net: dsa: move reset of VLAN filtering to dsa_port_switchdev_unsync_attrs
762c2998c962 Revert "net: dsa: setup master before ports"
8e6598a7b0fa net: dsa: Pass VLAN MSTI migration notifications to driver
332afc4c8c0d net: dsa: Validate hardware support for MST
f54fd0e16306 net: bridge: mst: Add helper to query a port's MST state
48d57b2e5f43 net: bridge: mst: Add helper to check if MST is enabled
cceac97afa09 net: bridge: mst: Add helper to map an MSTI to a VID set
7ae9147f4312 net: bridge: mst: Notify switchdev drivers of MST state changes
6284c723d9b9 net: bridge: mst: Notify switchdev drivers of VLAN MSTI migrations
87c167bb94ee net: bridge: mst: Notify switchdev drivers of MST mode changes
122c29486e1f net: bridge: mst: Support setting and reporting MST port states
8c678d60562f net: bridge: mst: Allow changing a VLAN's MSTI
ec7328b59176 net: bridge: mst: Multiple Spanning Tree (MST) mode
0832cd9f1f02 net: dsa: warn if port lists aren't empty in dsa_port_teardown
afb3cc1a397d net: dsa: unlock the rtnl_mutex when dsa_master_setup() fails
7569459a52c9 net: dsa: manage flooding on the CPU ports
499aa9e1b332 net: dsa: install the primary unicast MAC address as standalone port host FDB
5e8a1e03aa4d net: dsa: install secondary unicast and multicast addresses as host FDB/MDB
68d6d71eafd1 net: dsa: rename the host FDB and MDB methods to contain the "bridge" namespace
35aae5ab9121 net: dsa: remove workarounds for changing master promisc/allmulti only while up
06b9cce42634 net: dsa: pass extack to .port_bridge_join driver methods
c26933639b54 net: dsa: request drivers to perform FDB isolation
b6362bdf750b net: dsa: tag_8021q: rename dsa_8021q_bridge_tx_fwd_offload_vid
04b67e18ce5b net: dsa: tag_8021q: merge RX and TX VLANs
08f44db3abe6 net: dsa: felix: delete workarounds present due to SVL tag_8021q bridging
d27656d02d85 docs: net: dsa: sja1105: document limitations of tc-flower rule VLAN awareness
d7f9787a763f net: dsa: tag_8021q: add support for imprecise RX based on the VBID
91495f21fcec net: dsa: tag_8021q: replace the SVL bridging with VLAN-unaware IVL bridging
961d8b699070 net: dsa: felix: support FDB entries on offloaded LAG interfaces
e212fa7c5418 net: dsa: support FDB events on offloaded LAG interfaces
93c798230af5 net: dsa: call SWITCHDEV_FDB_OFFLOADED for the orig_dev
e35f12e993d4 net: dsa: remove "ds" and "port" from struct dsa_switchdev_event_work
ec638740fce9 net: switchdev: remove lag_mod_cb from switchdev_handle_fdb_event_to_device
dedd6a009f41 net: dsa: create a dsa_lag structure
b99dbdf00bc1 net: dsa: mv88e6xxx: use dsa_switch_for_each_port in mv88e6xxx_lag_sync_masks
3d4a0a2a46ab net: dsa: make LAG IDs one-based
066ce9779c7a net: dsa: qca8k: rename references to "lag" as "lag_dev"
e23eba722861 net: dsa: mv88e6xxx: rename references to "lag" as "lag_dev"
46a76724e4c9 net: dsa: rename references to "lag" as "lag_dev"
b9e8b58fd2cb net: dsa: Include BR_PORT_LOCKED in the list of synced brport flags
a21d9a670d81 net: bridge: Add support for bridge port in locked mode
acd8df5880d7 net: switchdev: avoid infinite recursion from LAG to bridge with port object handler
342b6419193c net: dsa: fix panic when removing unoffloaded port from bridge
8940e6b669ca net: dsa: avoid call to __dev_set_promiscuity() while rtnl_mutex isn't held
ba43b547515e net: lan966x: remove guards against !BRIDGE_VLAN_INFO_BRENTRY
e42bd4ed09aa net: mscc: ocelot: keep traps in a list
85ea0daabe5a net: mscc: ocelot: avoid overlap in VCAP IS2 between PTP and MRP traps
b9bace6e534d net: mscc: ocelot: use a single VCAP filter for all MRP traps
36fac35b2907 net: mscc: ocelot: delete OCELOT_MRP_CPUQ
c518afec2883 net: mscc: ocelot: consolidate cookie allocation for private VCAP rules
e3c02b7c655c net: mscc: ocelot: use a consistent cookie for MRP traps
164f861bd40c net: dsa: offload bridge port VLANs on foreign interfaces
134ef2388e7f net: dsa: add explicit support for host bridge VLANs
c4076cdd21f8 net: switchdev: introduce switchdev_handle_port_obj_{add,del} for foreign interfaces
7b465f4cf39e net: switchdev: rename switchdev_lower_dev_find to switchdev_lower_dev_find_rcu
b28d580e2939 net: bridge: switchdev: replay all VLAN groups
263029ae3172 net: bridge: make nbp_switchdev_unsync_objs() follow reverse order of sync()
8d23a54f5bee net: bridge: switchdev: differentiate new VLANs from changed ones
27c5f74c7ba7 net: bridge: vlan: notify switchdev only when something changed
cab2cd770051 net: bridge: vlan: make __vlan_add_flags react only to PVID and UNTAGGED
3116ad0696dd net: bridge: vlan: don't notify to switchdev master VLANs without BRENTRY flag
b2bc58d41fde net: bridge: vlan: check early for lack of BRENTRY flag in br_vlan_add_existing
ef5764057540 net: mscc: ocelot: fix use-after-free in ocelot_vlan_del()
5454f5c28eca net: bridge: vlan: check for errors from __vlan_del in __vlan_flush
867b1db874c9 net: lan966x: Fix when CONFIG_IPV6 is not set
1da52b0e4724 net: lan966x: Fix when CONFIG_PTP_1588_CLOCK is compiled as module
59085208e4a2 net: mscc: ocelot: fix all IP traffic getting trapped to CPU with PTP over IP
47aeea0d57e8 net: lan966x: Implement the callback SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED
cddbec19466a net: dsa: qca8k: add tracking state of master port
e83d56537859 net: dsa: replay master state events in dsa_tree_{setup,teardown}_master
295ab96f478d net: dsa: provide switch operations for tracking the master state
a1ff94c2973c net: dsa: stop updating master MTU from master.c
77eecf25bd9d net: lan966x: Update extraction/injection for timestamping
735fec995b21 net: lan966x: Implement SIOCSHWTSTAMP and SIOCGHWTSTAMP
d096459494a8 net: lan966x: Add support for ptp clocks
108dc8741c20 net: dsa: Avoid cross-chip syncing of VLAN filtering
381a730182f1 net: dsa: Move VLAN filtering syncing out of dsa_switch_bridge_leave
5cad43a52ee3 net: dsa: felix: add port fast age support
1b26d364e4e9 net: dsa: warn about dsa_port and dsa_switch bit fields being non atomic
63cfc65753d6 net: dsa: don't enumerate dsa_switch and dsa_port bit fields using commas
11fd667dac31 net: dsa: setup master before ports
1e3f407f3cac net: dsa: first set up shared ports, then non-shared ports
c146f9bc195a net: dsa: hold rtnl_mutex when calling dsa_master_{setup,teardown}
a68dc7b938fb net: dsa: remove cross-chip support for HSR
cad69019f2f8 net: dsa: remove cross-chip support for MRP
4b026e82893b net: dsa: combine two holes in struct dsa_switch_tree
b035c88c6a30 net: dsa: move dsa_switch_tree :: ports and lags to first cache line
258030acc93b net: dsa: make dsa_switch :: num_ports an unsigned int
7787ff776398 net: dsa: merge all bools of struct dsa_switch into a single u32
0625125877da net: dsa: move dsa_port :: type near dsa_port :: index
bde82f389af1 net: dsa: merge all bools of struct dsa_port into a single u8
b08db33dabd1 net: dsa: move dsa_port :: stp_state near dsa_port :: mac
7aacb894b1ad net: lan966x: Extend switchdev with mdb support
11b0a27772f5 net: lan966x: Add PGID_GP_START and PGID_GP_END
fc0c3fe7486f net: lan966x: Add function lan966x_mac_ip_learn()
0c94d657d2a4 net: lan966x: Fix the vlan used by host ports
2e49761e4fd1 net: lan966x: Add support for multiple bridge flags
811ba2771182 net: lan966x: Extend switchdev with fdb support
e14f72398df4 net: lan966x: Extend switchdev bridge flags
6d2c186afa5d net: lan966x: Add vlan support.
cf2f60897e92 net: lan966x: Add support to offload the forwarding.
571bb516a869 net: lan966x: Remove .ndo_change_rx_flags
25ee9561ec62 net: lan966x: More MAC table functionality
5ccd66e01cbe net: lan966x: add support for interrupts from analyzer
ef14049f4db9 net: lan966x: Add registers that are used for switch and vlan functionality
7f2973149c22 net: dsa: make tagging protocols connect to individual switches from a tree
e2f01bfe1406 net: dsa: tag_sja1105: fix zeroization of ds->priv on tag proto disconnect
b26980ab2a97 net: lan966x: Fix the configuration of the pcs
950a419d9de1 net: dsa: tag_sja1105: split sja1105_tagger_data into private and public sections
fcbf979a5b4b Revert "net: dsa: move sja1110_process_meta_tstamp inside the tagging protocol driver"
c79e84866d2a net: dsa: tag_sja1105: convert to tagger-owned data
22ee9f8e4011 net: dsa: sja1105: move ts_id from sja1105_tagger_data
bfcf14252220 net: dsa: sja1105: make dp->priv point directly to sja1105_tagger_data
6f6770ab1ce2 net: dsa: sja1105: remove hwts_tx_en from tagger data
d38049bbe760 net: dsa: sja1105: bring deferred xmit implementation in line with ocelot-8021q
a3d74295d790 net: dsa: sja1105: let deferred packets time out when sent to ports going down
35d976802124 net: dsa: tag_ocelot: convert to tagger-owned data
dc452a471dba net: dsa: introduce tagger-owned storage for private and shared data
857fdd74fb38 net: dsa: eliminate dsa_switch_ops :: port_bridge_tx_fwd_{,un}offload
b079922ba2ac net: dsa: add a "tx_fwd_offload" argument to ->port_bridge_join
d3eed0e57d5d net: dsa: keep the bridge_dev and bridge_num as part of the same structure
6a43cba30340 net: dsa: export bridging offload helpers to drivers
936db8a2dba2 net: dsa: rename dsa_port_offloads_bridge to dsa_port_offloads_bridge_dev
41fb0cf1bced net: dsa: hide dp->bridge_dev and dp->bridge_num in drivers behind helpers
36cbf39b5690 net: dsa: hide dp->bridge_dev and dp->bridge_num in the core behind helpers
65144067d360 net: dsa: mv88e6xxx: compute port vlan membership based on dp->bridge_dev comparison
0493fa7927af net: dsa: mv88e6xxx: iterate using dsa_switch_for_each_user_port in mv88e6xxx_port_check_hw_vlan
872bb81dfbc3 net: dsa: mt7530: iterate using dsa_switch_for_each_user_port in bridging ops
947c8746e2c3 net: dsa: assign a bridge number even without TX forwarding offload
3f9bb0301d50 net: dsa: make dp->bridge_num one-based
bb14bfc7eb92 net: lan966x: fix a IS_ERR() vs NULL check in lan966x_create_targets()
cc9cf69eea48 net: lan966x: Fix builds for lan966x driver
a290cf692779 net: lan966x: Fix duplicate check in frame extraction
12c2d0a5b8e2 net: lan966x: add ethtool configuration and statistics
e18aba8941b4 net: lan966x: add mactable support
d28d6d2e37d1 net: lan966x: add port module support
db8bcaad5393 net: lan966x: add the basic lan966x driver
ef136837aaf6 net: dsa: rtl8365mb: set RGMII RX delay in steps of 0.3 ns
b014861d96a6 net: dsa: realtek-smi: don't log an error on EPROBE_DEFER
1e89ad864d03 net: dsa: realtek-smi: fix indirect reg access for ports>3
b3612ccdf284 net: dsa: microchip: implement multi-bridge support
96ca08c05838 net: mscc: ocelot: set up traps for PTP packets
ec15baec3272 net: ptp: add a definition for the UDP port for IEEE 1588 general messages
95706be13b9f net: mscc: ocelot: create a function that replaces an existing VCAP filter
8abe19703825 net: dsa: felix: enable cut-through forwarding between ports by default
a8bd9fa5b527 net: ocelot: remove "bridge" argument from ocelot_get_bridge_fwd_mask
4636440f913b net: dsa: qca8k: Fix spelling mistake "Mismateched" -> "Mismatched"
0898ca67b86e net: dsa: qca8k: fix warning in LAG feature
def975307c01 net: dsa: qca8k: add LAG support
2c1bdbc7e756 net: dsa: qca8k: add support for mirror mode
ba8f870dfa63 net: dsa: qca8k: add support for mdb_add/del
6a3bdc5209f4 net: dsa: qca8k: add set_ageing_time support
4592538bfb0d net: dsa: qca8k: add support for port fast aging
c126f118b330 net: dsa: qca8k: add additional MIB counter and make it dynamic
8b5f3f29a81a net: dsa: qca8k: initial conversion to regmap helper
36b8af12f424 net: dsa: qca8k: move regmap init in probe and set it mandatory
994c28b6f971 net: dsa: qca8k: remove extra mutex_init in qca8k_setup
90ae68bfc2ff net: dsa: qca8k: convert to GENMASK/FIELD_PREP/FIELD_GET
b9133f3ef5a2 net: dsa: qca8k: remove redundant check in parse_port_config
65258b9d8cde net: dsa: qca8k: fix MTU calculation
3b00a07c2443 net: dsa: qca8k: fix internal delay applied to the wrong PAD config
a7e13edf37be net: dsa: felix: restrict psfp rules on ingress port
76c13ede7120 net: dsa: felix: use vcap policer to set flow meter for psfp
77043c37096d net: mscc: ocelot: use index to set vcap policer
23ae3a787771 net: dsa: felix: add stream gate settings for psfp
7d4b564d6add net: dsa: felix: support psfp filter on vsc9959
23e2c506ad6c net: mscc: ocelot: add gate and police action offload to PSFP
5b1918a54a91 net: mscc: ocelot: set vcap IS2 chain to goto PSFP chain
0568c3bf3f34 net: mscc: ocelot: add MAC table stream learn and lookup operations
02d6fdecb9c3 regmap: allow to define reg_update_bits for no bus configuration
5f15d392dcb4 net: dsa: qca8k: make sure PAD0 MAC06 exchange is disabled
ae0393500e3b net: bridge: switchdev: fix shim definition for br_switchdev_mdb_notify
326b212e9cd6 net: bridge: switchdev: consistent function naming
9776457c784f net: bridge: mdb: move all switchdev logic to br_switchdev.c
9ae9ff994b0e net: bridge: split out the switchdev portion of br_mdb_notify
4a6849e46173 net: bridge: move br_vlan_replay to br_switchdev.c
c5f6e5ebc2af net: bridge: provide shim definition for br_vlan_flags
716a30a97a52 net: switchdev: merge switchdev_handle_fdb_{add,del}_to_device
fab9eca88410 net: bridge: create a common function for populating switchdev FDB entries
5cda5272a460 net: bridge: move br_fdb_replay inside br_switchdev.c
9574fb558044 net: bridge: reduce indentation level in fdb_create
f6814fdcfe1b net: bridge: rename br_fdb_insert to br_fdb_add_local
4731b6d6b257 net: bridge: rename fdb_insert to fdb_add_local
5f94a5e276ae net: bridge: remove fdb_insert forward declaration
4682048af0c8 net: bridge: remove fdb_notify forward declaration
425d19cedef8 net: dsa: stop calling dev_hold in dsa_slave_fdb_event
d7d0d423dbaa net: dsa: flush switchdev workqueue when leaving the bridge
0faf890fc519 net: dsa: drop rtnl_lock from dsa_slave_switchdev_event_work
338a3a4745aa net: dsa: introduce locking for the address lists on CPU and DSA ports
cf231b436f7c net: dsa: lantiq_gswip: serialize access to the PCE registers
f7eb4a1c0864 net: dsa: b53: serialize access to the ARL table
edc90d15850c selftests: net: dsa: add a stress test for unlocked FDB operations
016748961ba5 selftests: lib: forwarding: allow tests to not require mz and jq
f239934cffe5 net: dsa: b53: serialize access to the ARL table
f2c4bdf62d76 net: mscc: ocelot: serialize access to the MAC table
1681ae1691ef net: dsa: sja1105: serialize access to the dynamic config interface
643979cf5ec4 net: dsa: sja1105: wait for dynamic config command completion on writes too
992e5cc7be8e net: dsa: tag_8021q: make dsa_8021q_{rx,tx}_vid take dp as argument
5068887a4fbe net: dsa: tag_sja1105: do not open-code dsa_switch_for_each_port
fac6abd5f132 net: dsa: convert cross-chip notifiers to iterate using dp
57d77986e742 net: dsa: remove gratuitous use of dsa_is_{user,dsa,cpu}_port
65c563a67755 net: dsa: do not open-code dsa_switch_for_each_port
d0004a020bb5 net: dsa: remove the "dsa_to_port in a loop" antipattern from the core
82b318983c51 net: dsa: introduce helpers for iterating through ports using dp
d4004422f6f9 net: mscc: ocelot: track the port pvid using a pointer
bfbab3104413 net: mscc: ocelot: add the local station MAC addresses in VID 0
0da1a1c48911 net: mscc: ocelot: allow a config where all bridge VLANs are egress-untagged
90e0aa8d108d net: mscc: ocelot: convert the VLAN masks to a list
62a22bcbd30e net: mscc: ocelot: add a type definition for REW_TAG_CFG_TAG_CFG
040e926f5813 net: dsa: qca8k: tidy for loop in setup and add cpu port check
9ca482a246f0 net: dsa: sja1105: parse {rx, tx}-internal-delay-ps properties for RGMII delays
4af2950c50c8 net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC
1521d5adfc2b net: dsa: tag_rtl8_4: add realtek 8 byte protocol 4 tag
9cb8edda2157 net: dsa: move NET_DSA_TAG_RTL4_A to right place in Kconfig/Makefile
7bbbbfaa7a1b ether: add EtherType for proprietary Realtek protocols
fd0bb28c547f net: dsa: qca8k: move port config to dedicated struct
cef08115846e net: dsa: qca8k: set internal delay also for sgmii
f477d1c8bdbe net: dsa: qca8k: add support for QCA8328
ed7988d77fbf dt-bindings: net: dsa: qca8k: document support for qca8328
362bb238d8bf net: dsa: qca8k: add support for pws config reg
924087c5c3d4 dt-bindings: net: dsa: qca8k: Document qca,led-open-drain binding
bbc4799e8bb6 net: dsa: qca8k: add explicit SGMII PLL enable
13ad5ccc093f dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll
5654ec78dd7e net: dsa: qca8k: rework rgmii delay logic and scan for cpu port 6
3fcf734aa482 net: dsa: qca8k: add support for cpu port 6
731d613338ec dt-bindings: net: dsa: qca8k: Document support for CPU port 6
6c43809bf1be net: dsa: qca8k: add support for sgmii falling edge
fdbf35df9c09 dt-bindings: net: dsa: qca8k: Add SGMII clock phase properties
d8b6f5bae6d3 dsa: qca8k: add mac_power_sel support
39e222bfd7f3 net: dsa: unregister cross-chip notifier after ds->ops->teardown
339e75f6b9a0 net: dsa: rtl8366rb: remove unneeded semicolon
e674cfd08537 net: dsa: rtl8366rb: Support setting STP state
1fbd19e10b73 net: dsa: rtl8366rb: Support fast aging
56d8bb71a811 net: dsa: rtl8366rb: Support disabling learning
5ca721c54d86 net: dsa: tag_ocelot: set the classified VLAN during xmit
e8c0722927e8 net: mscc: ocelot: write full VLAN TCI in the injection header
de5bbb6f7e4c net: mscc: ocelot: support egress VLAN rewriting via VCAP ES0
55b115c7ecd9 net: dsa: rtl8366rb: Use core filtering tracking
d310b14ae748 net: dsa: rtl8366: Drop and depromote pointless prints
a4eff910ec63 net: dsa: rtl8366rb: Rewrite weird VLAN filering enablement
7776e33c68ae net: dsa: rtl8366: Drop custom VLAN set-up
d5a680295be2 net: dsa: rtl8366rb: Support bridge offloading
bd936bd53b2d net: dsa: Move devlink registration to be last devlink command
6d709cadfde6 net: dsa: move sja1110_process_meta_tstamp inside the tagging protocol driver
68a81bb2eebd net: dsa: sja1105: remove sp->dp
db4278c55fa5 devlink: Make devlink_register to be void
4dcd183fbd67 net: wwan: iosm: devlink registration
From: Vladimir Oltean <vladimir.oltean@nxp.com> Date: 2022-09-06 16:40:59
On Tue, Sep 06, 2022 at 09:10:43AM -0700, Colin Foster wrote:
On Sun, Sep 04, 2022 at 07:34:14PM +0000, Vladimir Oltean wrote:
quoted
On Fri, Sep 02, 2022 at 08:44:37PM +0200, Christian Marangi wrote:
For transparency, here is the commit list I used to produce the backport (top-most is most recent):
Tangentially related: how did you come up with this list?
I can only assume this is a manual process based on intricate knowledge
of net / DSA as a whole. I just want to make sure there isn't a "git
backport net/dsa origin/master v5.10" sort of thing ;-)
Years of practice ;)
Although I found a tool called git-deps and I ran it in a few places,
I found it to be fundamentally lacking for correct kernel backporting
work. The way that tool works is it finds patches related to the current
one based on what other lines from this patch's context they touch.
This obviously isn't going to work too well. There may very well be no
connection obvious to this tool between, say, a function prototype added
to include/net/dsa.h and its first use in drivers/net/dsa/mv88e6xxx/chip.c.
So it may not know it has to backport the include/net/dsa.h change.
I suspect one way in which git-deps may be modified in order to be much
more useful for kernel work is for it to backport the entire patch
series from which the dependency commit came. But (1) I don't know
python even enough to be able to manage a pip virtual environment, let
alone code up such a change, and (2) I'm not sure, from a kernel devel
process perspective, that we offer enough machine-parsable hints such
that a python program can just figure out "yes, these are the patches
that all belong to the same patch set as commit X".