Thread (5 messages) 5 messages, 2 authors, 2022-07-29

Re: [PATCH net v1 1/1] net: dsa: microchip: don't try do read Gbit registers on non Gbit chips

From: Andrew Lunn <andrew@lunn.ch>
Date: 2022-07-28 13:25:55
Also in: lkml

On Thu, Jul 28, 2022 at 03:17:25PM +0200, Oleksij Rempel wrote:
quoted hunk ↗ jump to hunk
Do not try to read not existing or wrong register on chips without
GBIT_SUPPORT.

Fixes: c2e866911e25 ("net: dsa: microchip: break KSZ9477 DSA driver into two files")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
---
 drivers/net/dsa/microchip/ksz9477.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c
index c73bb6d383ad..f6bbd9646c85 100644
--- a/drivers/net/dsa/microchip/ksz9477.c
+++ b/drivers/net/dsa/microchip/ksz9477.c
@@ -316,7 +316,13 @@ void ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
 			break;
 		}
 	} else {
-		ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
+		/* No gigabit support.  Do not read wrong registers. */
+		if (!(dev->features & GBIT_SUPPORT) &&
+		    (reg == MII_CTRL1000 || reg == MII_ESTATUS ||
+		     reg == MII_STAT1000))
Does this actually happen?

If i remember this code correctly, it tries to make the oddly looking
PHY look like a normal PHY. phylib is then used to drive the PHY?

If i have that correct, why is phylib trying to read these registers?
It should know there is no 1G support, and should skip them.

   Andrew
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