[PATCH net-next 5/5] net: phy: add support to get Master-Slave configuration
From: Raju Lakkaraju <hidden>
Date: 2022-06-14 10:35:21
Also in:
lkml
Subsystem:
ethernet phy library, maxlinear ethernet phy driver, networking drivers, the rest · Maintainers:
Andrew Lunn, Heiner Kallweit, Xu Liang, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Implement reporting the Master-Slave configuration and state Signed-off-by: Raju Lakkaraju <redacted> --- drivers/net/phy/mxl-gpy.c | 55 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
diff --git a/drivers/net/phy/mxl-gpy.c b/drivers/net/phy/mxl-gpy.c
index 5ce1bf03bbd7..cf625ced4ec1 100644
--- a/drivers/net/phy/mxl-gpy.c
+++ b/drivers/net/phy/mxl-gpy.c@@ -27,11 +27,19 @@ #define PHY_ID_GPY241BM 0x67C9DE80 #define PHY_ID_GPY245B 0x67C9DEC0 +#define PHY_STD_GCTRL 0x09 /* Gbit ctrl */ +#define PHY_STD_GSTAT 0x0A /* Gbit status */ #define PHY_MIISTAT 0x18 /* MII state */ #define PHY_IMASK 0x19 /* interrupt mask */ #define PHY_ISTAT 0x1A /* interrupt status */ #define PHY_FWV 0x1E /* firmware version */ +#define PHY_STD_GCTRL_MS BIT(11) +#define PHY_STD_GCTRL_MSEN BIT(12) + +#define PHY_STD_GSTAT_MSRES BIT(14) +#define PHY_STD_GSTAT_MSFAULT BIT(15) + #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) #define PHY_MIISTAT_DPX BIT(3) #define PHY_MIISTAT_LS BIT(10)
@@ -160,6 +168,48 @@ static bool gpy_2500basex_chk(struct phy_device *phydev) return true; } +static int gpy_master_slave_cfg_get(struct phy_device *phydev) +{ + int state; + int cfg; + int ret; + + ret = phy_read(phydev, PHY_STD_GCTRL); + if (ret < 0) { + phydev_err(phydev, "Error: MDIO register access failed: %d\n", + ret); + return ret; + } + + if (ret & PHY_STD_GCTRL_MSEN) + if (ret & PHY_STD_GCTRL_MS) + cfg = MASTER_SLAVE_CFG_MASTER_FORCE; + else + cfg = MASTER_SLAVE_CFG_SLAVE_FORCE; + else + cfg = MASTER_SLAVE_CFG_MASTER_PREFERRED; + + ret = phy_read(phydev, PHY_STD_GSTAT); + if (ret < 0) { + phydev_err(phydev, "Error: MDIO register access failed: %d\n", + ret); + return ret; + } + + if (ret & PHY_STD_GSTAT_MSFAULT) + state = MASTER_SLAVE_STATE_ERR; + else + if (ret & PHY_STD_GSTAT_MSRES) + state = MASTER_SLAVE_STATE_MASTER; + else + state = MASTER_SLAVE_STATE_SLAVE; + + phydev->master_slave_get = cfg; + phydev->master_slave_state = state; + + return 0; +} + static bool gpy_sgmii_aneg_en(struct phy_device *phydev) { int ret;
@@ -295,6 +345,9 @@ static void gpy_update_interface(struct phy_device *phydev) ret); break; } + + if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) + gpy_master_slave_cfg_get(phydev); } static int gpy_read_status(struct phy_device *phydev)
@@ -309,6 +362,8 @@ static int gpy_read_status(struct phy_device *phydev) phydev->duplex = DUPLEX_UNKNOWN; phydev->pause = 0; phydev->asym_pause = 0; + phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; + phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { ret = genphy_c45_read_lpa(phydev);
--
2.25.1