Re: [PATCH bpf-next v3 2/4] arm64: insn: add encoders for atomic operations
From: Daniel Borkmann <daniel@iogearbox.net>
Date: 2022-02-11 14:40:04
Also in:
bpf, linux-arm-kernel
On 1/29/22 11:04 PM, Hou Tao wrote:
It is a preparation patch for eBPF atomic supports under arm64. eBPF
needs support atomic[64]_fetch_add, atomic[64]_[fetch_]{and,or,xor} and
atomic[64]_{xchg|cmpxchg}. The ordering semantics of eBPF atomics are
the same with the implementations in linux kernel.
Add three helpers to support LDCLR/LDEOR/LDSET/SWP, CAS and DMB
instructions. STADD/STCLR/STEOR/STSET are simply encoded as aliases for
LDADD/LDCLR/LDEOR/LDSET with XZR as the destination register, so no extra
helper is added. atomic_fetch_add() and other atomic ops needs support for
STLXR instruction, so extend enum aarch64_insn_ldst_type to do that.
LDADD/LDEOR/LDSET/SWP and CAS instructions are only available when LSE
atomics is enabled, so just return AARCH64_BREAK_FAULT directly in
these newly-added helpers if CONFIG_ARM64_LSE_ATOMICS is disabled.
Signed-off-by: Hou Tao <redacted>Hey Mark / Ard / Will / Catalin or others, could we get an Ack on patch 1 & 2 at min if it looks good to you? Thanks a lot, Daniel