On 12/13/21 6:43 AM, David Laight wrote:
There is no need to special case the very unusual odd-aligned buffers.
They are no worse than 4n+2 aligned buffers.
Signed-off-by: David Laight <redacted>
---
On an i7-7700 misaligned buffers add 2 or 3 clocks (in 115) to a 512 byte
checksum.
That is just measuring the main loop with an lfence prior to rdpmc to
read PERF_COUNT_HW_CPU_CYCLES.
I'm a bit confused by this changelog.
Are you saying that the patch causes a (small) performance regression?
Are you also saying that the optimization here is not worth it because
it saves 15 lines of code? Or that the misalignment checks themselves
add 2 or 3 cycles, and this is an *optimization*?