Sean, Russell,
On 26/10/2021 at 20:52, Sean Anderson wrote:
quoted
Going back to the first point I mentioned above, how much should we
take from these documents as actually being correct? Should we not
assume anything, but instead just experiment with the hardware and
see what works.
For example, are the two speed bits in the PCS control register
really read-only when in Cisco SGMII mode, or can they be changed -
and if they can be changed, does that have an effect on the ethernet
link?
Keep in mind that it is not only Zynq(MP) parts with have GEMs, but
several other SoCs as well. I have not reviewed their datasheets (except
for SiFive's which just say "go read the Linux driver"). It is possible
that other SoCs may not have these limitations. So any experimental
program will need to also experiment with e.g. sama.
Claudiu and myself can certainly help in reviewing and testing on
Microchip devices. The limitation that I see is that we only have 10/100
and 1000 speeds implemented in our SoC with limited number of link types
covered (MII, RMII, GMII and RGMII).
Our datasheets including different variants of MACB and GEM can give
some information:
MACB example in:
http://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Data-Sheet-DS60001579A.pdf
GEM example at 10/100 in:
https://www.microchip.com/content/dam/mchp/documents/MPU32/ProductDocuments/DataSheets/SAMA5D2-Series-Data-sheet-ds60001476G.pdf
GEM example with 10/100/1000 in:
https://www.microchip.com/content/dam/mchp/documents/MPU32/ProductDocuments/DataSheets/SAMA5D3-Series-Data-sheet-DS60001609b.pdf
We can also explore some of the design and configuration registers (DCFGn).
Perhaps someone from cadence could comment on what is actually supported
by gem/macb?
That could be good as well.
Best regards,
Nicolas
--
Nicolas Ferre