On 2021/8/23 20:42, Ilias Apalodimas wrote:
On Mon, Aug 23, 2021 at 11:56:48AM +0800, Yunsheng Lin wrote:
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On 2021/8/20 17:39, Ilias Apalodimas wrote:
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On Fri, Aug 20, 2021 at 02:56:51PM +0800, Yunsheng Lin wrote:
[..]
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https://elixir.bootlin.com/linux/latest/source/kernel/dma/direct.h#L104
The one thing I am not sure about is that the pool->p.offset
and pool->p.max_len are used to decide the sync range before this
patch, while the sync range is the same as the map range when doing
the sync in dma_map_page_attrs().
I am not sure I am following here. We always sync the entire range as well
in the current code as the mapping function is called with max_len.
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I assumed the above is not a issue? only sync more than we need?
and it won't hurt the performance?
We can sync more than we need, but if it's a non-coherent architecture,
there's a performance penalty.
Since I do not have any performance data to prove if there is a
performance penalty for non-coherent architecture, I will drop it:)
Regards
/Ilias
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