Re: [PATCH] net: marvell: fix MVNETA_TX_IN_PRGRS bit number
From: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Date: 2021-08-06 14:29:31
Also in:
lkml
Hello, On Fri, 6 Aug 2021 17:04:37 +0300 Maksim [off-list ref] wrote:
quoted hunk ↗ jump to hunk
According to Armada XP datasheet bit at 0 position is corresponding for TxInProg indication. Signed-off-by: Maksim <redacted> --- drivers/net/ethernet/marvell/mvneta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 76a7777c746da..de32e5b49053b 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c@@ -105,7 +105,7 @@ #define MVNETA_VLAN_PRIO_TO_RXQ 0x2440 #define MVNETA_VLAN_PRIO_RXQ_MAP(prio, rxq) ((rxq) << ((prio) * 3)) #define MVNETA_PORT_STATUS 0x2444 -#define MVNETA_TX_IN_PRGRS BIT(1) +#define MVNETA_TX_IN_PRGRS BIT(0) #define MVNETA_TX_FIFO_EMPTY BIT(8) #define MVNETA_RX_MIN_FRAME_SIZE 0x247c /* Only exists on Armada XP and Armada 370 */
Indeed, I just checked the datasheet, and it's bit 0 in this register that indicates if transmit is in progress. The only function using this is mvneta_port_down(), which polls until MVNETA_TX_FIFO_EMPTY is set and MVNETA_TX_IN_PRGRS is cleared in this register. Bit 1 in this register is marked as reserved, read-only and read as zero, so I suppose that mvneta_port_down() was basically never waiting for MVNETA_TX_IN_PRGRS to clear. Have you seen some actual visible issue, or was this just found by code inspection ? Best regards, Thomas -- Thomas Petazzoni, co-owner and CEO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com