From: Subbaraya Sundeep <sbhatta@marvell.com>
'bp_ena' in Aura context is NIX block index, setting it
zero will always backpressure NIX0 block, even if NIXLF
belongs to NIX1. Hence fix this by setting it appropriately
based on NIX block address.
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: Hariprasad Kelam <redacted>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
@@ -1190,7 +1190,22 @@ static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id,/* Enable backpressure for RQ aura */if(aura_id<pfvf->hw.rqpool_cnt&&!is_otx2_lbkvf(pfvf->pdev)){aq->aura.bp_ena=0;+/* If NIX1 LF is attached then specify NIX1_RX.+*+*BelowNPA_AURA_S[BP_ENA]issetaccordingtothe+*NPA_BPINTF_Eenumerationgivenas:+*0x0+a*0x1where'a'is0forNIX0_RXand1forNIX1_RXso+*NIX0_RXis0x0+0*0x1=0+*NIX1_RXis0x0+1*0x1=1+*ButinHRMitisgiventhat+*"NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to+*NIX-RXbasedon[BP]level.OnebitperNIX-RX;index+*enumeratedbyNPA_BPINTF_E."+*/+if(pfvf->nix_blkaddr==BLKADDR_NIX1)+aq->aura.bp_ena=1;aq->aura.nix0_bpid=pfvf->bpid[0];+/* Set backpressure level for RQ's Aura */aq->aura.bp=RQ_BP_LVL_AURA;}
From: Subbaraya Sundeep <sbhatta@marvell.com>
As per hardware the base channel number configured
for programmable channels of a block must be multiple
of number of channels of that block. This condition
is not met for SDP base channel currently. Hence this
patch ensures all the base channel numbers of all
blocks are multiple of number of channels present in
the blocks. Also instead of hardcoding SDP number
of channels the same is read from the NIX_AF_CONST1
register.
Fixes: 242da439214b ("octeontx2-af: cn10k: Add support for programmable")
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/af/common.h | 2 --
.../net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 31 +++++++++++++++-------
2 files changed, 22 insertions(+), 11 deletions(-)
@@ -222,6 +223,7 @@ int rvu_set_channels_base(struct rvu *rvu)returnblkaddr;nix_const=rvu_read64(rvu,blkaddr,NIX_AF_CONST);+nix_const1=rvu_read64(rvu,blkaddr,NIX_AF_CONST1);hw->cgx=(nix_const>>12)&0xFULL;hw->lmac_per_cgx=(nix_const>>8)&0xFULL;
@@ -244,14 +246,24 @@ int rvu_set_channels_base(struct rvu *rvu)*channelssuchthatallchannelnumbersarecontiguous*leavingnoholes.ThiswaythenewCPTchannelscanbe*accomodated.Theorderofchannelnumbersassignedis-*LBK,SDP,CGXandCPT.+*LBK,SDP,CGXandCPT.Alsothebasechannelnumber+*ofablockmustbemultipleofnumberofchannels+*oftheblock.*/-hw->sdp_chan_base=hw->lbk_chan_base+hw->lbk_links*-((nix_const>>16)&0xFFULL);-hw->cgx_chan_base=hw->sdp_chan_base+hw->sdp_links*SDP_CHANNELS;+nr_lbk_chans=(nix_const>>16)&0xFFULL;+nr_sdp_chans=nix_const1&0xFFFULL;+nr_cgx_chans=nix_const&0xFFULL;+nr_cpt_chans=(nix_const>>32)&0xFFFULL;-cpt_chan_base=hw->cgx_chan_base+hw->cgx_links*-(nix_const&0xFFULL);+sdp_chan_base=hw->lbk_chan_base+hw->lbk_links*nr_lbk_chans;+/* Round up base channel to multiple of number of channels */+hw->sdp_chan_base=ALIGN(sdp_chan_base,nr_sdp_chans);++cgx_chan_base=hw->sdp_chan_base+hw->sdp_links*nr_sdp_chans;+hw->cgx_chan_base=ALIGN(cgx_chan_base,nr_cgx_chans);++cpt_chan_base=hw->cgx_chan_base+hw->cgx_links*nr_cgx_chans;+hw->cpt_chan_base=ALIGN(cpt_chan_base,nr_cpt_chans);/* Out of 4096 channels start CPT from 2048 so*thatMSBforCPTchannelsisalwaysset
From: Hariprasad Kelam <redacted>
Supported link modes are updated by firmware in shared
structure per interface. Kernel uses this value to display
supported link modes via ethtool.
Currently there is extra validation that firmware updated
modes are validated against internal list of supported modes.
As intenal list of supported modes are not updated frequently
new modes supported by firmware are not updated to ethtool.
Hence remove extra validation and report all firmware updated
modes.
Signed-off-by: Hariprasad Kelam <redacted>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c | 5 -----
1 file changed, 5 deletions(-)
From: Geetha sowjanya <gakula@marvell.com>
CN10K platform requires physically contiguous memory for LMTST
operations which goes beyond a single page. Not having physically
contiguous memory will result in HW fetching transmit descriptors from
a wrong memory location.
Hence use DMA_ATTR_FORCE_CONTIGUOUS attribute while allocating
LMTST regions.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/af/common.h | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
From: Geetha sowjanya <gakula@marvell.com>
Bandwidth profiles (ipolicer structure)is implemented only on CN10K
platform. But current code try to free the ipolicer memory without
checking the capibility flag leading to driver crash on OCTEONTX2
platform. This patch fixes the issue by add capability flag check.
Fixes: e8e095b3b3700 ("octeontx2-af: cn10k: Bandwidth profiles config support")
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
Whenever user changes interface MAC address both default DMAC based
MCAM rule and VLAN offload (for strip) rules are updated with new
MAC address. To update or install VLAN offload rule PF driver needs
interface's receive channel info, which is retrieved from admin
function at the time of NIXLF initialization.
If user changes MAC address before interface is UP, VLAN offload rule
installation will fail and throw error as receive channel is not valid.
To avoid this, skip VLAN offload rule installation if netdev is not UP.
This rule will anyway be reinslatted as part of open() call.
Fixes: fd9d7859db6c ("octeontx2-pf: Implement ingress/egress VLAN offload")
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
@@ -208,7 +208,8 @@ int otx2_set_mac_address(struct net_device *netdev, void *p)if(!otx2_hw_set_mac_addr(pfvf,addr->sa_data)){memcpy(netdev->dev_addr,addr->sa_data,netdev->addr_len);/* update dmac field in vlan offload rule */-if(pfvf->flags&OTX2_FLAG_RX_VLAN_SUPPORT)+if(netif_running(netdev)&&+pfvf->flags&OTX2_FLAG_RX_VLAN_SUPPORT)otx2_install_rxvlan_offload_flow(pfvf);/* update dmac address in ntuple and DMAC filter list */if(pfvf->flags&OTX2_FLAG_DMACFLTR_SUPPORT)
Otherthan setting action as RSS in NPC MCAM entry, RSS flowkey
algorithm index also needs to be set. Otherwise whatever algorithm
is defined at flowkey index '0' will be considered by HW and pkt
flows will be distributed as such.
Fix this by saving the flowkey index sent by admin function while
initializing RSS and then use it when framing MCAM rules.
Fixes: 81a4362016e7 ("octeontx2-pf: Add RSS multi group support")
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c | 11 +++++++++++
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h | 3 +++
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c | 1 +
3 files changed, 15 insertions(+)
Hello:
This series was applied to netdev/net-next.git (refs/heads/master):
On Sun, 22 Aug 2021 17:32:17 +0530 you wrote:
This patch series contains a bunch of miscellaneous fixes
for various issues like
- Free unallocated memory during driver unload
- HW reading transmit descriptor from wrong address
- VF VLAN strip offload MCAM entry installation failure
- Pkts not being distributed across queues in RSS context
- Wrong interface backpressure configuration for NIX1 block on 98xx
- etc
[...]