Re: [PATCH net-next] net: axienet: Allow phytool access to PCS/PMA PHY

Allow phytool ioctl access to read/write registers in the internal
PCS/PMA PHY if it is enabled.

Signed-off-by: Robert Hancock <redacted>
---
 .../net/ethernet/xilinx/xilinx_axienet_main.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 13cd799541aa..41f2c2255118 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c

@@ -1213,10 +1213,29 @@ static void axienet_poll_controller(struct net_device *ndev)
 static int axienet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
 	struct axienet_local *lp = netdev_priv(dev);
+	struct mii_ioctl_data *mii = if_mii(rq);
 
 	if (!netif_running(dev))
 		return -EINVAL;
 
+	if (lp->pcs_phy && lp->pcs_phy->addr == mii->phy_id) {
+		int ret;
+
+		switch (cmd) {
+		case SIOCGMIIREG:
+			ret = mdiobus_read(lp->pcs_phy->bus, mii->phy_id, mii->reg_num);
+			if (ret >= 0) {
+				mii->val_out = ret;
+				ret = 0;
+			}
+			return ret;
+
+		case SIOCSMIIREG:
+			return mdiobus_write(lp->pcs_phy->bus, mii->phy_id,
+					     mii->reg_num, mii->val_in);
+		}