Re: [PATCH net-next v2 0/2] Enable 2.5Gbps speed for stmmac

quoted

You have a MAC and an PCS in the stmmac IP block. That then has
some
sort of SERDES interface, running 1000BaseX, SGMII, SGMII
overclocked
at 2.5G or 25000BaseX. Connected to the SERDES you have a PHY
which
converts to copper, giving you 2500BaseT.

You said earlier, that the PHY can only do 2500BaseT. So it should
be
the PHY driver which sets supported to 2500BaseT and no other
speeds.

You should think about when somebody uses this MAC with a
different
PHY, one that can do the full range of 10/half through to 2.5G
full. What generally happens is that the PHY performs auto-neg to
determine the link speed. For 10M-1G speeds the PHY will
configure its
SERDES interface to SGMII and phylink will ask the PCS to also be
configured to SGMII. If the PHY negotiates 2500BaseT, it will
configure its side of the SERDES to 2500BaseX or SGMII
overclocked at
2.5G. Again, phylink will ask the PCS to match what the PHY is
doing.

So, where exactly is the limitation in your hardware? PCS or PHY?

The limitation in the hardware is at the PCS side where it is either running
in SGMII 2.5G or SGMII 1G speeds.
When running on SGMII 2.5G speeds, we disable the in-band AN and use 2.5G speed only

So there is no actual limitation! The MAC should indicate it can do
10Half through to 2500BaseT. And you need to listen to PHYLINK and
swap the PCS between SGMII to overclocked SGMII when it requests.

PHYLINK will call stmmac_mac_config() and use state->interface to
decide how to configure the PCS to match what the PHY is doing.

     Andrew