Thread (6 messages) flat view 6 messages, 2 authors, 2021-02-13
STALE2017d

Revision v1 of 3 in this series.

Revisions (3)
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  2. v2 [diff vs current]
  3. v3 [diff vs current]

[PATCH net-next 0/2] ptp: ptp_clockmatrix: Fix output 1 PPS alignment.

From: <hidden>
Date: 2021-02-12 05:07:37
Also in: lkml

From: Vincent Cheng <redacted>

This series fixes a race condition that may result in the output clock
not aligned to internal 1 PPS clock.

Part of device initialization is to align the rising edge of output
clocks to the internal rising edge of the 1 PPS clock.  If the system
APLL and DPLL are not locked when this alignment occurs, the alignment
fails and a fixed offset between the internal 1 PPS clock and the
output clock occurs.

If a clock is dynamically enabled after power-up, the output clock
also needs to be aligned to the internal 1 PPS clock.

Vincent Cheng (2):
  ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.
  ptp: ptp_clockmatrix: Add alignment of 1 PPS to idtcm_perout_enable.

 drivers/ptp/idt8a340_reg.h    | 10 +++++
 drivers/ptp/ptp_clockmatrix.c | 92 ++++++++++++++++++++++++++++++++++++++++---
 drivers/ptp/ptp_clockmatrix.h | 17 +++++++-
 3 files changed, 112 insertions(+), 7 deletions(-)

-- 
2.7.4
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