Re: [PATCH net-next] net: dsa: microchip: Adjust reset release timing to match reference reset circuit

On 1/19/2021 6:01 PM, Marek Vasut wrote:

KSZ8794CNX datasheet section 8.0 RESET CIRCUIT describes recommended
circuit for interfacing with CPU/FPGA reset consisting of 10k pullup
resistor and 10uF capacitor to ground. This circuit takes ~100 mS to
rise enough to release the reset.

For maximum supply voltage VDDIO=3.3V VIH=2.0V R=10kR C=10uF that is
                    VDDIO - VIH
  t = R * C * -ln( ------------- ) = 10000*0.00001*-(-0.93)=0.093 S
                       VDDIO
so we need ~95 mS for the reset to really de-assert, and then the
original 100uS for the switch itself to come out of reset. Simply
msleep() for 100 mS which fits the constraint with a bit of extra
space.

This is nitpicking but the unit symbol for seconds is 's', not 'S' which
is for Siemens.

With that fixed:

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian