For common stmmac:
- Add support to set CSR Clock range selection in DT
For stm32mpu:
- Glue codes to support magic packet
- Glue codes to support all PHY config :
PHY_MODE (MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config
For stm32mcu:
- Add Ethernet support for stm32h7
- Add syscfg clk support for stm32f4
Changes in V2:
Apply remarks from andrew lunn
- add all interfaces RGMII*
- reg value should be the same as ethernet-phy@X
Christophe Roullier (8):
net: ethernet: stmmac: manage Ethernet WoL for stm32mp157c.
net: ethernet: stmmac: update to support all PHY config for
stm32mp157c.
dt-bindings: net: stmmac: add phys config properties
net: ethernet: stmmac: add management of clk_csr property
net: ethernet: stmmac: update to be compatible with MCU family
(stm32f4, stm32h7)
dt-bindings: net: stmmac: add syscfg clock property
ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it
for eval and disco boards
ARM: dts: stm32: add syscfg clock support for Ethernet on STM32F429
SoC
.../devicetree/bindings/net/stm32-dwmac.txt | 10 +-
arch/arm/boot/dts/stm32f429.dtsi | 6 +-
arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 15 ++
arch/arm/boot/dts/stm32h743.dtsi | 19 +++
arch/arm/boot/dts/stm32h743i-disco.dts | 17 ++
arch/arm/boot/dts/stm32h743i-eval.dts | 17 ++
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 182 +++++++++++++++++----
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +
8 files changed, 233 insertions(+), 36 deletions(-)
--
2.7.4
Need syscfg clock for MCU family in case bootloader does not
activate it.
Signed-off-by: Christophe Roullier <redacted>
---
Documentation/devicetree/bindings/net/stm32-dwmac.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
@@ -14,8 +14,8 @@ Required properties: - clock-names: Should be "stmmaceth" for the host clock. Should be "mac-clk-tx" for the MAC TX clock. Should be "mac-clk-rx" for the MAC RX clock.- For MPU family need to add also "ethstp" for power mode clock and,- "syscfg-clk" for SYSCFG clock.+ Should be "syscfg-clk" for the SYSCFG clock.+ For MPU family need to add also "ethstp" for power mode clock - interrupt-names: Should contain a list of interrupt names corresponding to the interrupts in the interrupts property, if available. Should be "macirq" for the main MAC IRQ
This patch add syscfg clock support for Ethernet of the STM32F429 SoC.
Needed if bootloader do not manage it.
Signed-off-by: Christophe Roullier <redacted>
---
arch/arm/boot/dts/stm32f429.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
Update glue codes to support all PHY config on stm32mp157c
PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config.
Signed-off-by: Christophe Roullier <redacted>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 105 +++++++++++++++++-----
1 file changed, 85 insertions(+), 20 deletions(-)
@@ -154,6 +211,11 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)return-EINVAL;}+/* Need to update PMCCLRR (clear register) */+ret=regmap_write(dwmac->regmap,reg+SYSCFG_PMCCLRR_OFFSET,+dwmac->ops->syscfg_eth_mask);++/* Update PMCSETR (set register) */returnregmap_update_bits(dwmac->regmap,reg,dwmac->ops->syscfg_eth_mask,val);}
@@ -237,22 +299,25 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,structdevice_node*np=dev->of_node;interr=0;-dwmac->int_phyclk=of_property_read_bool(np,"st,int-phyclk");+/* Gigabit Ethernet 125MHz clock selection. */+dwmac->eth_clk_sel_reg=of_property_read_bool(np,"st,eth_clk_sel");-/* Check if internal clk from RCC selected */-if(dwmac->int_phyclk){-/* Get ETH_CLK clocks */-dwmac->clk_eth_ck=devm_clk_get(dev,"eth-ck");-if(IS_ERR(dwmac->clk_eth_ck)){-dev_err(dev,"No ETH CK clock provided...\n");-returnPTR_ERR(dwmac->clk_eth_ck);-}+/* Ethernet 50Mhz RMII clock selection */+dwmac->eth_ref_clk_sel_reg=+of_property_read_bool(np,"st,eth_ref_clk_sel");++/* Get ETH_CLK clocks */+dwmac->clk_eth_ck=devm_clk_get(dev,"eth-ck");+if(IS_ERR(dwmac->clk_eth_ck)){+dev_warn(dev,"No phy clock provided...\n");+dwmac->clk_eth_ck=NULL;}/* Clock used for low power mode */dwmac->clk_ethstp=devm_clk_get(dev,"ethstp");if(IS_ERR(dwmac->clk_ethstp)){-dev_err(dev,"No ETH peripheral clock provided for CStop mode ...\n");+dev_err(dev,+"No ETH peripheral clock provided for CStop mode ...\n");returnPTR_ERR(dwmac->clk_ethstp);}
@@ -268,7 +333,7 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,*/dwmac->irq_pwr_wakeup=platform_get_irq_byname(pdev,"stm32_pwr_wakeup");-if(!dwmac->int_phyclk&&dwmac->irq_pwr_wakeup>=0){+if(!dwmac->clk_eth_ck&&dwmac->irq_pwr_wakeup>=0){err=device_init_wakeup(&pdev->dev,true);if(err){dev_err(&pdev->dev,"Failed to init wake up irq\n");
@@ -370,7 +435,7 @@ static int stm32mp1_suspend(struct stm32_dwmac *dwmac)clk_disable_unprepare(dwmac->clk_tx);clk_disable_unprepare(dwmac->syscfg_clk);-if(dwmac->int_phyclk)+if(dwmac->clk_eth_ck)clk_disable_unprepare(dwmac->clk_eth_ck);returnret;
Add properties to support all Phy config
PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config.
Signed-off-by: Christophe Roullier <redacted>
---
Documentation/devicetree/bindings/net/stm32-dwmac.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
@@ -24,9 +24,9 @@ Required properties: encompases the glue register, and the offset of the control register. Optional properties:-- clock-names: For MPU family "mac-clk-ck" for PHY without quartz-- st,int-phyclk (boolean) : valid only where PHY do not have quartz and need to be clock- by RCC+- clock-names: For MPU family "eth-ck" for PHY without quartz+- st,eth_clk_sel (boolean) : set this property in RGMII PHY when you do not want use 125Mhz+- st,eth_ref_clk_sel (boolean) : set this property in RMII mode when you have PHY without crystal 50MHz Example:
@@ -42,6 +42,7 @@ struct stm32_dwmac {structclk*clk_ethstp;structclk*syscfg_clk;boolint_phyclk;/* Clock from RCC to drive PHY */+intirq_pwr_wakeup;u32mode_reg;/* MAC glue-logic mode register */structregmap*regmap;u32speed;
@@ -232,7 +233,9 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,staticintstm32mp1_parse_data(structstm32_dwmac*dwmac,structdevice*dev){+structplatform_device*pdev=to_platform_device(dev);structdevice_node*np=dev->of_node;+interr=0;dwmac->int_phyclk=of_property_read_bool(np,"st,int-phyclk");
@@ -260,7 +263,26 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,returnPTR_ERR(dwmac->syscfg_clk);}-return0;+/* Get IRQ information early to have an ability to ask for deferred+*probeifneededbeforewewenttoofarwithresourceallocation.+*/+dwmac->irq_pwr_wakeup=platform_get_irq_byname(pdev,+"stm32_pwr_wakeup");+if(!dwmac->int_phyclk&&dwmac->irq_pwr_wakeup>=0){+err=device_init_wakeup(&pdev->dev,true);+if(err){+dev_err(&pdev->dev,"Failed to init wake up irq\n");+returnerr;+}+err=dev_pm_set_dedicated_wake_irq(&pdev->dev,+dwmac->irq_pwr_wakeup);+if(err){+dev_err(&pdev->dev,"Failed to set wake up irq\n");+device_init_wakeup(&pdev->dev,false);+}+device_set_wakeup_enable(&pdev->dev,false);+}+returnerr;}staticintstm32_dwmac_probe(structplatform_device*pdev)
@@ -326,9 +348,15 @@ static int stm32_dwmac_remove(struct platform_device *pdev)structnet_device*ndev=platform_get_drvdata(pdev);structstmmac_priv*priv=netdev_priv(ndev);intret=stmmac_dvr_remove(&pdev->dev);+structstm32_dwmac*dwmac=priv->plat->bsp_priv;stm32_dwmac_clk_disable(priv->plat->bsp_priv);+if(dwmac->irq_pwr_wakeup>=0){+dev_pm_clear_wake_irq(&pdev->dev);+device_init_wakeup(&pdev->dev,false);+}+returnret;}
In Documentation stmmac.txt there is possibility to
fixed CSR Clock range selection with property clk_csr.
This patch add the management of this property
For example to use it, add in your ethernet node DT:
clk_csr = <3>;
Signed-off-by: Christophe Roullier <redacted>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +++
1 file changed, 3 insertions(+)
@@ -408,6 +408,9 @@ stmmac_probe_config_dt(struct platform_device *pdev, const char **mac)/* Default to phy auto-detection */plat->phy_addr=-1;+/* Get clk_csr from device tree */+of_property_read_u32(np,"clk_csr",&plat->clk_csr);+/* "snps,phy-addr" is not a standard property. Mark it as deprecated*andwarnofitsuse.Removethiswhenphynodesupportisadded.*/
From: Rob Herring <robh@kernel.org> Date: 2019-02-23 00:16:55
On Fri, Feb 22, 2019 at 09:28:04AM +0100, Christophe Roullier wrote:
quoted hunk
Add properties to support all Phy config
PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config.
Signed-off-by: Christophe Roullier <redacted>
---
Documentation/devicetree/bindings/net/stm32-dwmac.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
@@ -24,9 +24,9 @@ Required properties: encompases the glue register, and the offset of the control register. Optional properties:-- clock-names: For MPU family "mac-clk-ck" for PHY without quartz-- st,int-phyclk (boolean) : valid only where PHY do not have quartz and need to be clock- by RCC
You can't just remove properties.
+- clock-names: For MPU family "eth-ck" for PHY without quartz
+- st,eth_clk_sel (boolean) : set this property in RGMII PHY when you do not want use 125Mhz
+- st,eth_ref_clk_sel (boolean) : set this property in RMII mode when you have PHY without crystal 50MHz
s/_/-/
'sel' I assume is short for select, but the naming here and description
don't really tell me what I'm getting.
Rob
From: Rob Herring <robh@kernel.org> Date: 2019-02-23 00:19:04
On Fri, 22 Feb 2019 09:28:07 +0100, Christophe Roullier wrote:
Need syscfg clock for MCU family in case bootloader does not
activate it.
Signed-off-by: Christophe Roullier <redacted>
---
Documentation/devicetree/bindings/net/stm32-dwmac.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
On Fri, Feb 22, 2019 at 09:28:04AM +0100, Christophe Roullier wrote:
quoted
Add properties to support all Phy config
PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config.
Signed-off-by: Christophe Roullier <redacted>
---
Documentation/devicetree/bindings/net/stm32-dwmac.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
@@ -24,9 +24,9 @@ Required properties: encompases the glue register, and the offset of the control register. Optional properties:-- clock-names: For MPU family "mac-clk-ck" for PHY without quartz-- st,int-phyclk (boolean) : valid only where PHY do not have quartz and need to be clock- by RCC
You can't just remove properties.
There is no risk to remove/rename these 2 properties, because it is
specific board which is never deployed.
With new properties (renaming clock (eth-ck) + st,eth_clk_sel and
st,eth_ref_clk_sel, we are managed all kind of specific boards stm32mp1
So no risk of backward compatible.
quoted
+- clock-names: For MPU family "eth-ck" for PHY without quartz
+- st,eth_clk_sel (boolean) : set this property in RGMII PHY when you do not want use 125Mhz
+- st,eth_ref_clk_sel (boolean) : set this property in RMII mode when you have PHY without crystal 50MHz
s/_/-/
'sel' I assume is short for select, but the naming here and description
don't really tell me what I'm getting.