Thread (52 messages) 52 messages, 6 authors, 2019-02-14

Re: [PATCH] net: phylink: dsa: mv88e6xxx: Revise irq setup ordering

From: Andrew Lunn <andrew@lunn.ch>
Date: 2019-02-04 19:35:28

On Mon, Feb 04, 2019 at 01:37:13PM -0500, John David Anglin wrote:
This change fixes a race condition in the setup of hardware irqs and the
code enabling PHY link
detection.

This was observed on the espressobin board where the GPIO interrupt
controller only supports edge
interrupts.  If the INTn output pin goes low before the GPIO interrupt
is enabled, PHY link interrupts
are not detected.
Hi David

Please break this up into two patches.

Masking interrupts in the setup code before enabling the interrupt i'm
happy with.

The change to the interrupt handler i'm pretty sure is wrong. You have
to accept with edge interrupts you are going to loose interrupts.

    Andrew
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