On Thu, Nov 30, 2017 at 12:26 AM, Florian Fainelli [off-list ref] wrote:

On 11/29/2017 03:19 PM, Linus Walleij wrote:

quoted

Or are there in pracice things such that reg is different
on the port and the PHY connected to it? Then it makes
much sense to put an MDIO bus inside the switch DT
node and populate the PHY interrupts from there as you
say.

Yes, I have such systems here, Port 0 has its PHY at MDIO address 5 for
instance.

That explains it.

switch@0 {
        compatible = "acme,switch";
        #address-cells = <1>;
        #size-cells = <0>;

        ports {

                port@0 {
                        reg = <0>;
                        phy-handle = <&phy0>;
                };

                port@1 {
                        reg = <1>;
                        phy-handle = <&phy1>;
                };

                port@8 {
                        reg = <8>;
                        ethernet = = <&eth0>;
                };
        };

        mdio {
                compatible = "acme,switch-mdio";

                phy@0 {
                        reg = <0>;
                };

                phy@1 {
                        reg = <1>;
                };
        };
};

That way it's clear which port maps to which PHY, and that the MDIO
controller is internal within the switch (and so are the PHYs).

So why not:

switch@0 {
        compatible = "acme,switch";
        #address-cells = <1>;
        #size-cells = <0>;

        ports {

                port@0 {
                        reg = <0>;
                        phy@0 {
                             reg = <0>;
                        };
                };

                port@1 {
                        reg = <1>;
                        phy@1 {
                             reg = <1>;
                        };
                };

                port@8 {
                        reg = <8>;
                        ethernet = = <&eth0>;
                };
        };

This avoids the cross-referencing of phandles.

Yours,
Linus Walleii