Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register.

On 14.9.2017 16:34, Andrew Lunn wrote:

On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote:

quoted

To clear Speed Selection in MDIO control register(0x10),
ie, clear bits 6 and 13 to zero while keeping other bits same.
Before AND operation,The Mask value has to be perform with bitwise NOT
operation (ie, ~ operator)

This patch clears current speed selection before writing the
new speed settings to gmii2rgmii converter

Hi Fahad

I expect you will find other issues with this driver. I pointed some
out at the time it is submitted, but the developers went quiet as soon
as it was accepted.

Can you please point me to that email?
I will create ticket about it in our system to get them resolved.

Thanks,
Michal