From: Simon Horman <hidden> Date: 2017-01-27 11:05:50
Hi,
this series adds support for gigabit communication to the Renesas EthernetAVB
controller when used in conjunction with R-Car Gen3 H3 ES1.1+ and M3-W SoCs.
Gigabit is already supported with R-Car Gen 2 SoCs.
The patch from Geert was previously posted for inclusion in v4.10 and
acked by Dave for that purpose. It was, however, not accepted by the
ARM SoC maintainers.
The path from Mizuguchi-san is to address timing problems observed with
gigabit transfers. I would like it considered although my own testing on
M3-W did not show any timing problems.
Geert Uytterhoeven (1):
ravb: Support 1Gbps on R-Car H3 ES1.1+ and R-Car M3-W
Kazuya Mizuguchi (1):
ravb: Add tx and rx clock internal delays mode of APSR
drivers/net/ethernet/renesas/ravb.h | 10 ++++++++
drivers/net/ethernet/renesas/ravb_main.c | 39 ++++++++++++++++++++++++++++++--
2 files changed, 47 insertions(+), 2 deletions(-)
--
2.7.0.rc3.207.g0ac5344
From: Simon Horman <hidden> Date: 2017-01-27 11:05:32
From: Geert Uytterhoeven <geert+renesas@glider.be>
The limitation to 10/100Mbit speeds on R-Car Gen3 is valid for R-Car H3
ES1.0 only. Check for the exact SoC model to allow 1Gbps on newer
revisions of R-Car H3, and on R-Car M3-W.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <redacted>
---
drivers/net/ethernet/renesas/ravb_main.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
@@ -1008,10 +1014,10 @@ static int ravb_phy_init(struct net_device *ndev)gotoerr_deregister_fixed_link;}-/* This driver only support 10/100Mbit speeds on Gen3+/* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0*atthistime.*/-if(priv->chip_id==RCAR_GEN3){+if(soc_device_match(r8a7795es10)){err=phy_set_max_speed(phydev,SPEED_100);if(err){netdev_err(ndev,"failed to limit PHY to 100Mbit/s\n");
From: Simon Horman <hidden> Date: 2017-01-27 11:06:15
From: Kazuya Mizuguchi <redacted>
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <redacted>
Signed-off-by: Simon Horman <redacted>
---
v1 [Simon Horman]
- Combined patches
- Reworded changelog
v0 [Kazuya Mizuguchi]
---
drivers/net/ethernet/renesas/ravb.h | 10 ++++++++++
drivers/net/ethernet/renesas/ravb_main.c | 29 +++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
Hi Simon,
On Fri, Jan 27, 2017 at 12:04 PM, Simon Horman
[off-list ref] wrote:
The path from Mizuguchi-san is to address timing problems observed with
gigabit transfers. I would like it considered although my own testing on
M3-W did not show any timing problems.
Is there any relation with the *-skew-ps properties in the DTS in the BSP?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
From: Sergei Shtylyov <hidden> Date: 2017-01-27 12:43:21
Hello!
On 01/27/2017 02:04 PM, Simon Horman wrote:
quoted hunk
From: Kazuya Mizuguchi <redacted>
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <redacted>
Signed-off-by: Simon Horman <redacted>
---
v1 [Simon Horman]
- Combined patches
- Reworded changelog
v0 [Kazuya Mizuguchi]
---
drivers/net/ethernet/renesas/ravb.h | 10 ++++++++++
drivers/net/ethernet/renesas/ravb_main.c | 29 +++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
From: Sergei Shtylyov <hidden> Date: 2017-01-27 12:53:10
On 01/27/2017 02:04 PM, Simon Horman wrote:
From: Geert Uytterhoeven <geert+renesas@glider.be>
The limitation to 10/100Mbit speeds on R-Car Gen3 is valid for R-Car H3
ES1.0 only. Check for the exact SoC model to allow 1Gbps on newer
revisions of R-Car H3, and on R-Car M3-W.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <redacted>
From: Sergei Shtylyov <hidden> Date: 2017-01-27 13:00:32
On 01/27/2017 02:04 PM, Simon Horman wrote:
From: Kazuya Mizuguchi <redacted>
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <redacted>
Signed-off-by: Simon Horman <redacted>
---
v1 [Simon Horman]
- Combined patches
- Reworded changelog
v0 [Kazuya Mizuguchi]
@@ -2016,6 +2039,9 @@ static int ravb_probe(struct platform_device *pdev)/* Request GTI loading */ravb_modify(ndev,GCCR,GCCR_LTI,GCCR_LTI);+/* Set APSR */+ravb_set_delay_mode(ndev);+/* Allocate descriptor base address table */priv->desc_bat_size=sizeof(structravb_desc)*DBAT_ENTRY_NUM;priv->desc_bat=dma_alloc_coherent(ndev->dev.parent,priv->desc_bat_size,
@@ -2152,6 +2178,9 @@ static int __maybe_unused ravb_resume(struct device *dev)/* Request GTI loading */ravb_modify(ndev,GCCR,GCCR_LTI,GCCR_LTI);+/* Set APSR */+ravb_set_delay_mode(ndev);+
So far the pattern was to first check if gen != 2, then calling a gen3
specific function. I'd like to keep it, rather than checking in the function
itself.
[...]
MBR, Sergei
From: Simon Horman <horms@verge.net.au> Date: 2017-01-27 16:34:52
On Fri, Jan 27, 2017 at 01:16:43PM +0100, Geert Uytterhoeven wrote:
Hi Simon,
On Fri, Jan 27, 2017 at 12:04 PM, Simon Horman
[off-list ref] wrote:
quoted
The path from Mizuguchi-san is to address timing problems observed with
gigabit transfers. I would like it considered although my own testing on
M3-W did not show any timing problems.
Is there any relation with the *-skew-ps properties in the DTS in the BSP?
Yes, I believe they are also intended to address timeouts.
I plan to post them too.
From: Simon Horman <horms@verge.net.au> Date: 2017-01-27 16:49:28
On Fri, Jan 27, 2017 at 03:42:05PM +0300, Sergei Shtylyov wrote:
Hello!
On 01/27/2017 02:04 PM, Simon Horman wrote:
quoted
From: Kazuya Mizuguchi <redacted>
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <redacted>
Signed-off-by: Simon Horman <redacted>
---
v1 [Simon Horman]
- Combined patches
- Reworded changelog
v0 [Kazuya Mizuguchi]
---
drivers/net/ethernet/renesas/ravb.h | 10 ++++++++++
drivers/net/ethernet/renesas/ravb_main.c | 29 +++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
Something like this?
int set = 0;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
set |= APSR_DM_RDM;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
set |= APSR_DM_TDM;
ravb_modify(ndev, APSR, APSR_DM, set);
I don't really see any advantage to it but I can change things around
however you like.
From: Simon Horman <horms@verge.net.au> Date: 2017-01-27 16:51:29
On Fri, Jan 27, 2017 at 04:00:27PM +0300, Sergei Shtylyov wrote:
On 01/27/2017 02:04 PM, Simon Horman wrote:
quoted
From: Kazuya Mizuguchi <redacted>
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <redacted>
Signed-off-by: Simon Horman <redacted>
---
v1 [Simon Horman]
- Combined patches
- Reworded changelog
v0 [Kazuya Mizuguchi]
So far the pattern was to first check if gen != 2, then calling a gen3
specific function. I'd like to keep it, rather than checking in the function
itself.
So you would like something like?
/* Set APSR */
if (priv->chip_id != RCAR_GEN2)
ravb_set_delay_mode(ndev);
That does not seem better to me but I can make it so if that is your
preference.
From: Sergei Shtylyov <hidden> Date: 2017-01-27 17:45:48
On 01/27/2017 07:51 PM, Simon Horman wrote:
quoted
quoted
From: Kazuya Mizuguchi <redacted>
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <redacted>
Signed-off-by: Simon Horman <redacted>
---
v1 [Simon Horman]
- Combined patches
- Reworded changelog
v0 [Kazuya Mizuguchi]
So far the pattern was to first check if gen != 2, then calling a gen3
specific function. I'd like to keep it, rather than checking in the function
itself.
So you would like something like?
/* Set APSR */
if (priv->chip_id != RCAR_GEN2)
ravb_set_delay_mode(ndev);
Yes (except the comment).
That does not seem better to me but I can make it so if that is your
preference.
Yes, not better code-wise but more consistent.
MBR, Sergei
From: Sergei Shtylyov <hidden> Date: 2017-01-27 18:01:08
On 01/27/2017 07:49 PM, Simon Horman wrote:
quoted
quoted
From: Kazuya Mizuguchi <redacted>
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <redacted>
Signed-off-by: Simon Horman <redacted>
---
v1 [Simon Horman]
- Combined patches
- Reworded changelog
v0 [Kazuya Mizuguchi]
---
drivers/net/ethernet/renesas/ravb.h | 10 ++++++++++
drivers/net/ethernet/renesas/ravb_main.c | 29 +++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
Something like this?
int set = 0;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
set |= APSR_DM_RDM;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
set |= APSR_DM_TDM;
ravb_modify(ndev, APSR, APSR_DM, set);
I don't really see any advantage to it but I can change things around
however you like.
I didn't mean to replace *switch*, actually -- just to move ravb_modify()
out of it.
MBR, Sergei
From: Simon Horman <horms@verge.net.au> Date: 2017-01-27 18:07:10
On Fri, Jan 27, 2017 at 07:55:25PM +0300, Sergei Shtylyov wrote:
On 01/27/2017 07:49 PM, Simon Horman wrote:
quoted
quoted
quoted
From: Kazuya Mizuguchi <redacted>
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <redacted>
Signed-off-by: Simon Horman <redacted>
---
v1 [Simon Horman]
- Combined patches
- Reworded changelog
v0 [Kazuya Mizuguchi]
---
drivers/net/ethernet/renesas/ravb.h | 10 ++++++++++
drivers/net/ethernet/renesas/ravb_main.c | 29 +++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
Something like this?
int set = 0;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
set |= APSR_DM_RDM;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
set |= APSR_DM_TDM;
ravb_modify(ndev, APSR, APSR_DM, set);
I don't really see any advantage to it but I can change things around
however you like.
I didn't mean to replace *switch*, actually -- just to move ravb_modify()
out of it.
From: Sergei Shtylyov <hidden> Date: 2017-01-27 18:12:49
On 01/27/2017 09:07 PM, Simon Horman wrote:
quoted
quoted
quoted
quoted
From: Kazuya Mizuguchi <redacted>
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <redacted>
Signed-off-by: Simon Horman <redacted>
---
v1 [Simon Horman]
- Combined patches
- Reworded changelog
v0 [Kazuya Mizuguchi]
---
drivers/net/ethernet/renesas/ravb.h | 10 ++++++++++
drivers/net/ethernet/renesas/ravb_main.c | 29 +++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
Something like this?
int set = 0;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
set |= APSR_DM_RDM;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
set |= APSR_DM_TDM;
ravb_modify(ndev, APSR, APSR_DM, set);
I don't really see any advantage to it but I can change things around
however you like.
I didn't mean to replace *switch*, actually -- just to move ravb_modify()
out of it.
Ok, I will make it so.
Your variant is probably even better! :-)
I'm not sure how good gcc is at merging the similar code paths,
simplifying its work seems worth it to me. The less repetitive code, the better.
MBR, Sergei
From: Simon Horman <horms@verge.net.au> Date: 2017-01-27 18:22:18
On Fri, Jan 27, 2017 at 09:11:35PM +0300, Sergei Shtylyov wrote:
On 01/27/2017 09:07 PM, Simon Horman wrote:
quoted
quoted
quoted
quoted
quoted
From: Kazuya Mizuguchi <redacted>
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <redacted>
Signed-off-by: Simon Horman <redacted>
---
v1 [Simon Horman]
- Combined patches
- Reworded changelog
v0 [Kazuya Mizuguchi]
---
drivers/net/ethernet/renesas/ravb.h | 10 ++++++++++
drivers/net/ethernet/renesas/ravb_main.c | 29 +++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
Something like this?
int set = 0;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
set |= APSR_DM_RDM;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
set |= APSR_DM_TDM;
ravb_modify(ndev, APSR, APSR_DM, set);
I don't really see any advantage to it but I can change things around
however you like.
I didn't mean to replace *switch*, actually -- just to move ravb_modify()
out of it.
Ok, I will make it so.
Your variant is probably even better! :-)
I'm not sure how good gcc is at merging the similar code paths,
simplifying its work seems worth it to me. The less repetitive code, the
better.