Re: [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly

On 2016年11月28日 17:22, Nicolas Ferre wrote:

Le 28/11/2016 à 08:57, Zumeng Chen a écrit :

quoted

When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:

   <write ~MACB_BIT(RE)>
   + wmb();
   <write MACB_BIT(RE)>

There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.

Signed-off-by: Zumeng Chen <redacted>
---
  drivers/net/ethernet/cadence/macb.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 533653b..2f9c5b2 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c

@@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
  		if (status & MACB_BIT(RXUBR)) {
  			ctrl = macb_readl(bp, NCR);
  			macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
+			wmb();
  			macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
  
  			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)

It seems that there is exactly the same pattern in function
at91ether_interrupt() can you fix both locations in your patch please?

Indeed, I'll send v2 soon, thanks Nicolas.

Although I only have the environment to re-produce the error report
as follows: "not whole frame pointed by descriptor" for macb_interrupt.

Cheers,
Zumeng

Thanks, best regards,