On Fri, Nov 25, 2016 at 05:49:45PM +0100, Christian Borntraeger wrote:
On 11/25/2016 05:17 PM, Peter Zijlstra wrote:
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On Fri, Nov 25, 2016 at 04:10:04PM +0000, Mark Rutland wrote:
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On Fri, Nov 25, 2016 at 04:21:39PM +0100, Dmitry Vyukov wrote:
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What are use cases for such primitive that won't be OK with "read once
_and_ atomically"?
I have none to hand.
Whatever triggers the __builtin_memcpy() paths, and even the size==8
paths on 32bit.
You could put a WARN in there to easily find them.
There were several cases that I found during writing the *ONCE stuff.
For example there are some 32bit ppc variants with 64bit PTEs. Some for
others (I think sparc).
We have similar on 32-bit ARM w/ LPAE. LPAE implies that a naturally
aligned 64-bit access is single-copy atomic, which is what makes that
ok.
And the mm/ code is perfectly fine with these PTE accesses being done
NOT atomic.
That strikes me as surprising. Is there some mutual exclusion that
prevents writes from occuring wherever a READ_ONCE() happens to a PTE?
Otherwise, how is tearing not a problem? Does it have some pattern like
the lockref cmpxchg?
Thanks,
Mark.