Thread (17 messages) 17 messages, 7 authors, 2016-11-30

Re: [PATCH net-next v2 3/4] Documentation: net: phy: Add blurb about RGMII

From: Florian Fainelli <f.fainelli@gmail.com>
Date: 2016-11-28 19:47:47

On 11/28/2016 11:15 AM, Mason wrote:
On 28/11/2016 18:43, Florian Fainelli wrote:
quoted
On 11/28/2016 02:34 AM, Sebastian Frias wrote:
quoted
For what is worth, the Atheros at803x driver comes with RX delay enabled
as per HW reset.
Always, or is this a behavior possibly defined via a stra-pin that can
be changed?
Here's the data sheet:

  http://www.redeszone.net/app/uploads/2014/04/AR8035.pdf

4.2.25 rgmii rx clock delay control
Offset: 0x00
bit 15: Control bit for rgmii interface rx clock delay:
1 = rgmii rx clock delay enable
0 = rgmii rx clock delay disable
HW Rst. 1
SW Rst. 1

As far as I can tell, rx delay is enabled by default, always.

The "Features" list mentions
"RGMII timing modes support internal delay and external delay on Rx path"
(Not sure about the internal vs external distinction.)

Table 3-6. RGMII AC Characteristics — no Internal Delay
Table 3-7. RGMII AC Characteristics — with internal delay added (Default)

Delay is 2 ns apparently.

There's also
4.2.27 Hib ctrl and rgmii gtx clock delay register
Offset: 0x0B

bits 6:5 Gtx_dly_val
Select the delay of gtx_clk.
00:0.25ns
01:1.3ns
10:2.4ns
11:3.4ns

I don't know what that is used for.
Maybe this is the external vs internal delay?
First, this has little to do with the initial patch series being
discussed now, and second, this still looks like an internal delay
programming, just that it applies to the received transmit clock from
the MAC, that's how I read it though.
-- 
Florian
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