Thread (3 messages) flat view 3 messages, 2 authors, 2016-10-03

Re: [PATCH 3/3] net: smsc911x: add u16 workaround for pxa platforms

From: Mark Rutland <mark.rutland@arm.com>
Date: 2016-10-03 16:51:11
Also in: linux-devicetree, lkml

On Mon, Oct 03, 2016 at 06:11:23PM +0200, Robert Jarzmik wrote:
Mark Rutland [off-list ref] writes:
quoted
On Mon, Oct 03, 2016 at 11:05:53AM +0200, Robert Jarzmik wrote:
quoted
Add a workaround for mainstone, idp and stargate2 boards, for u16 writes
which must be aligned on 32 bits addresses.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 Documentation/devicetree/bindings/net/smsc911x.txt | 2 ++
 1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/smsc911x.txt b/Documentation/devicetree/bindings/net/smsc911x.txt
index 3fed3c124411..224965b7453c 100644
--- a/Documentation/devicetree/bindings/net/smsc911x.txt
+++ b/Documentation/devicetree/bindings/net/smsc911x.txt
@@ -13,6 +13,8 @@ Optional properties:
 - reg-io-width : Specify the size (in bytes) of the IO accesses that
   should be performed on the device.  Valid value for SMSC LAN is
   2 or 4.  If it's omitted or invalid, the size would be 2.
+- reg-u16-align4 : Boolean, put in place the workaround the force all
+  		   u16 writes to be 32 bits aligned
This property name and description is confusing.

How exactly does this differ from having reg-io-width = <4>, which is
documented immediately above?
reg-io-width specifies the IO size, ie. how many data lines are physically
connected from the system bus to the lan adapter.

reg-u16-align4 tells that a specific hardware doesn't support 16 bit writes not
being 32 bits aligned, or said differently that a "store" 16 bits wide on an
address of the format 4*n + 2 deserves a special handling in the driver, while a
store 16 bits wide on an address of the format 4*n can follow the simple casual
case.
If I've understood correctly, effectively the low 2 address lines to the
device are hard-wired to zero, e.g. a 16-bit access to 4*n + 2 would go
to 4*n + 0 on the device? Or is the failure case distinct from that?

Do we have other platforms where similar is true? e.g. u8 accesses
requiring 16-bit alignment?

Thanks,
Mark.
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