From: Sean Wang <sean.wang@mediatek.com>
By default, GMAC0 is connected to built-in switch called
MT7530 through the proprietary interface called Turbo RGMII
(TRGMII). TRGMII also supports well for RGMII as generic external
PHY uses but requires some slight changes to the setup of TRGMII
and doesn't have well support on current driver.
So this patchset
1) provides the slight changes of the setup for RGMII can work
through TRGMII
2) adds additional setting "trgmii" about phy-mode on device tree
to make GMAC0 distinguish which mode it runs
3) changes dynamically source clock, TX/RX delay and interface
mode on TRGMII for adapting various link
Sean Wang (3):
net: ethernet: mediatek: add extension of phy-mode for TRGMII
net: ethernet: mediatek: add support for GMAC0 connecting with
external PHY through TRGMII
net: ethernet: mediatek: add the dts property to set if TRGMII
supported on GMAC0
.../devicetree/bindings/net/mediatek-net.txt | 5 +-
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 57 ++++++++++++++++++++--
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 32 ++++++++++++
3 files changed, 90 insertions(+), 4 deletions(-)
--
1.9.1
From: Sean Wang <sean.wang@mediatek.com>
Add the dts property for the capability if TRGMII supported on GAMC0
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
@@ -31,7 +31,10 @@ Optional properties: Required properties: - compatible: Should be "mediatek,eth-mac" - reg: The number of the MAC-- phy-handle: see ethernet.txt file in the same directory.+- phy-handle: see ethernet.txt file in the same directory and+ the additional phy-mode "tgrmii" is provided in order to connect+ with the internal switch MT7530 which is only applicable when reg+ is equal to 0. Example:
From: Sean Wang <sean.wang@mediatek.com>
Changing dynamically source clock, TX/RX delay and interface mode
used by TRGMII hardware module inside PHY capability polling routine
for adapting to the various speed of RGMII used by external PHY for
GMAC0.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 33 ++++++++++++++++++++++++++++-
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 29 +++++++++++++++++++++++++
2 files changed, 61 insertions(+), 1 deletion(-)
@@ -135,6 +135,33 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)return_mtk_mdio_read(eth,phy_addr,phy_reg);}+staticvoidmtk_gmac0_rgmii_adjust(structmtk_eth*eth,intspeed)+{+u32val;+intret;++val=(speed==SPEED_1000)?+INTF_MODE_RGMII_1000:INTF_MODE_RGMII_10_100;+mtk_w32(eth,val,INTF_MODE);++regmap_update_bits(eth->ethsys,ETHSYS_CLKCFG0,+ETHSYS_TRGMII_CLK_SEL362_5,+ETHSYS_TRGMII_CLK_SEL362_5);++val=(speed==SPEED_1000)?250000000:500000000;+ret=clk_set_rate(eth->clks[MTK_CLK_TRGPLL],val);+if(ret)+dev_err(eth->dev,"Failed to set trgmii pll: %d\n",ret);++val=(speed==SPEED_1000)?+RCK_CTRL_RGMII_1000:RCK_CTRL_RGMII_10_100;+mtk_w32(eth,val,TRGMII_RCK_CTRL);++val=(speed==SPEED_1000)?+TCK_CTRL_RGMII_1000:TCK_CTRL_RGMII_10_100;+mtk_w32(eth,val,TRGMII_TCK_CTRL);+}+staticintmtk_of_get_phy_mode(structmtk_mac*mac,structdevice_node*np){intphy_mode,err;
@@ -149,6 +176,7 @@ static int mtk_of_get_phy_mode(struct mtk_mac *mac, struct device_node *np)returnerr;if(!strcasecmp(pm,"trgmii")){mac->trgmii=true;+/* TRGMII could be compatible with RGMII */returnPHY_INTERFACE_MODE_RGMII;}else
From: Andrew Lunn <andrew@lunn.ch> Date: 2016-09-20 19:38:09
On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote:
quoted hunk
From: Sean Wang <sean.wang@mediatek.com>
Add the dts property for the capability if TRGMII supported on GAMC0
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
@@ -31,7 +31,10 @@ Optional properties: Required properties: - compatible: Should be "mediatek,eth-mac" - reg: The number of the MAC-- phy-handle: see ethernet.txt file in the same directory.+- phy-handle: see ethernet.txt file in the same directory and+ the additional phy-mode "tgrmii" is provided in order to connect+ with the internal switch MT7530 which is only applicable when reg+ is equal to 0.
Humm. How is the switch connected? Is it on the MDIO bus?
If it is on the mdio bus, the binding is going to look something like:
eth: ethernet@1b100000 {
compatible = "mediatek,mt7623-eth";
reg = <0 0x1b100000 0 0x20000>;
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
<ðsys CLK_ETHSYS_ESW>,
<ðsys CLK_ETHSYS_GP2>,
<ðsys CLK_ETHSYS_GP1>;
clock-names = "ethif", "esw", "gp2", "gp1";
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
resets = <ðsys MT2701_ETHSYS_ETH_RST>;
reset-names = "eth";
mediatek,ethsys = <ðsys>;
mediatek,pctl = <&syscfg_pctl_a>;
#address-cells = <1>;
#size-cells = <0>;
gmac1: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
};
gmac2: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
};
mdio-bus {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
switch0: switch0@0 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
...
...
In this case the switch is an MDIO device, not an PHY. It will not
have an phy-mode. It cannot have a phy mode, it is not a PHY.
Or am i missing something here?
Thanks
Andrew
On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote:
quoted
From: Sean Wang <sean.wang@mediatek.com>
Add the dts property for the capability if TRGMII supported on GAMC0
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
@@ -31,7 +31,10 @@ Optional properties: Required properties: - compatible: Should be "mediatek,eth-mac" - reg: The number of the MAC-- phy-handle: see ethernet.txt file in the same directory.+- phy-handle: see ethernet.txt file in the same directory and+ the additional phy-mode "tgrmii" is provided in order to connect+ with the internal switch MT7530 which is only applicable when reg+ is equal to 0.
Humm. How is the switch connected? Is it on the MDIO bus?
the switch is connected to MDIO bus
If it is on the mdio bus, the binding is going to look something like:
eth: ethernet@1b100000 {
compatible = "mediatek,mt7623-eth";
reg = <0 0x1b100000 0 0x20000>;
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
<ðsys CLK_ETHSYS_ESW>,
<ðsys CLK_ETHSYS_GP2>,
<ðsys CLK_ETHSYS_GP1>;
clock-names = "ethif", "esw", "gp2", "gp1";
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
resets = <ðsys MT2701_ETHSYS_ETH_RST>;
reset-names = "eth";
mediatek,ethsys = <ðsys>;
mediatek,pctl = <&syscfg_pctl_a>;
#address-cells = <1>;
#size-cells = <0>;
gmac1: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
};
gmac2: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
};
mdio-bus {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
switch0: switch0@0 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
...
...
In this case the switch is an MDIO device, not an PHY. It will not
have an phy-mode. It cannot have a phy mode, it is not a PHY.
Or am i missing something here?
Thanks
1)
The switch driver is not supported for DSA so far yet
but DSA is good thing and I will try make it happen
in the near future.
And another question about DSA, that is
if I use DSA for switch, how to know the relationship
between MAC and DSA ? such like I could know relationship
between MAC and PHY by phy-handle.
The cause I ask is becasue I think it's good if the topology
about MAC/PHYs/Switch is known just by dts files.
2)
The phy-mode I mention is for fixed-link. For current MAC driver,
it just uses fixed phy to adapt into the part of switch, so the
device tree looks something like the below.
ð {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-handle = <&phy5>;
};
On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote:
quoted
From: Sean Wang <sean.wang@mediatek.com>
Add the dts property for the capability if TRGMII supported on GAMC0
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
@@ -31,7 +31,10 @@ Optional properties: Required properties: - compatible: Should be "mediatek,eth-mac" - reg: The number of the MAC-- phy-handle: see ethernet.txt file in the same directory.+- phy-handle: see ethernet.txt file in the same directory and+ the additional phy-mode "tgrmii" is provided in order to connect+ with the internal switch MT7530 which is only applicable when reg+ is equal to 0.
Humm. How is the switch connected? Is it on the MDIO bus?
the switch is connected to MDIO bus
quoted
If it is on the mdio bus, the binding is going to look something like:
eth: ethernet@1b100000 {
compatible = "mediatek,mt7623-eth";
reg = <0 0x1b100000 0 0x20000>;
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
<ðsys CLK_ETHSYS_ESW>,
<ðsys CLK_ETHSYS_GP2>,
<ðsys CLK_ETHSYS_GP1>;
clock-names = "ethif", "esw", "gp2", "gp1";
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
resets = <ðsys MT2701_ETHSYS_ETH_RST>;
reset-names = "eth";
mediatek,ethsys = <ðsys>;
mediatek,pctl = <&syscfg_pctl_a>;
#address-cells = <1>;
#size-cells = <0>;
gmac1: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
};
gmac2: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
};
mdio-bus {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
switch0: switch0@0 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
...
...
In this case the switch is an MDIO device, not an PHY. It will not
have an phy-mode. It cannot have a phy mode, it is not a PHY.
Or am i missing something here?
Thanks
1)
The switch driver is not supported for DSA so far yet
but DSA is good thing and I will try make it happen
in the near future.
O.K. But if i understand correctly, the TRGMII is so you can use the
switch. So it needs to work when you have DSA.
And another question about DSA, that is
if I use DSA for switch, how to know the relationship
between MAC and DSA ? such like I could know relationship
between MAC and PHY by phy-handle.
It will look like what i stated above. But i missed the cpu node in
the ports, which is what you are asking about. There will also be a
node like:
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac1>;
};
And this is how you couple the MAC to DSA.
The cause I ask is becasue I think it's good if the topology
about MAC/PHYs/Switch is known just by dts files.
2)
The phy-mode I mention is for fixed-link. For current MAC driver,
it just uses fixed phy to adapt into the part of switch, so the
device tree looks something like the below.
ð {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-handle = <&phy5>;
};
static int mtk_phy_connect(struct mtk_mac *mac)
{
struct mtk_eth *eth = mac->hw;
struct device_node *np;
u32 val;
np = of_parse_phandle(mac->of_node, "phy-handle", 0);
if (!np && of_phy_is_fixed_link(mac->of_node))
if (!of_phy_register_fixed_link(mac->of_node))
np = of_node_get(mac->of_node);
...
...
mtk_phy_connect_node(eth, mac, np);
So in the case of a fixed-phy, you do look in the MAC node, and when
there is a phy-handle, you look in the PHY node.
So this does work....
Andrew
On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote:
quoted
From: Sean Wang <sean.wang@mediatek.com>
Add the dts property for the capability if TRGMII supported on GAMC0
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
.... deleted
quoted
quoted
In this case the switch is an MDIO device, not an PHY. It will not
have an phy-mode. It cannot have a phy mode, it is not a PHY.
Or am i missing something here?
Thanks
1)
The switch driver is not supported for DSA so far yet
but DSA is good thing and I will try make it happen
in the near future.
O.K. But if i understand correctly, the TRGMII is so you can use the
switch. So it needs to work when you have DSA.
yes, you are right. TRGMII for now is dedicated for switch
and furthermore it needs doing calibration between the host and
the switch before it works, that I expect to put
the logic of calibration into setup callback of DSA driver.
quoted
And another question about DSA, that is
if I use DSA for switch, how to know the relationship
between MAC and DSA ? such like I could know relationship
between MAC and PHY by phy-handle.
It will look like what i stated above. But i missed the cpu node in
the ports, which is what you are asking about. There will also be a
node like:
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac1>;
};
And this is how you couple the MAC to DSA.
thanks, it is answerig my question : i can get the relationship from
the node of cpu port pointing to what MAC it runs for.
quoted
The cause I ask is becasue I think it's good if the topology
about MAC/PHYs/Switch is known just by dts files.
2)
The phy-mode I mention is for fixed-link. For current MAC driver,
it just uses fixed phy to adapt into the part of switch, so the
device tree looks something like the below.
ð {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-handle = <&phy5>;
};
static int mtk_phy_connect(struct mtk_mac *mac)
{
struct mtk_eth *eth = mac->hw;
struct device_node *np;
u32 val;
np = of_parse_phandle(mac->of_node, "phy-handle", 0);
if (!np && of_phy_is_fixed_link(mac->of_node))
if (!of_phy_register_fixed_link(mac->of_node))
np = of_node_get(mac->of_node);
...
...
mtk_phy_connect_node(eth, mac, np);
So in the case of a fixed-phy, you do look in the MAC node, and when
there is a phy-handle, you look in the PHY node.
So this does work....