Re: [PATCH net-next 01/19] net: hns: bug fix of ge reset sequence
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: 2016-06-21 10:36:12
Also in:
linux-arm-kernel, lkml
On Tue, 2016-06-21 at 11:56 +0800, Yisen Zhuang wrote:
quoted hunk ↗ jump to hunk
From: Qianqian Xie <redacted> The bit fileds of PPE reset register are different between HNS v1 and HNS v2, but the current procedure just only match HNS v1. Here is a patch to fix it. Signed-off-by: Kejian Yan <redacted> Signed-off-by: Qianqian Xie <redacted> Signed-off-by: Yisen Zhuang <redacted> --- drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.cb/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c index 96cb628..09e60d6 100644--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c@@ -271,7 +271,11 @@ static void hns_dsaf_ge_srst_by_port(structdsaf_device *dsaf_dev, u32 port, } } else { reg_val_1 = 0x15540 << dsaf_dev->reset_offset; - reg_val_2 = 0x100 << dsaf_dev->reset_offset; + + if (AE_IS_VER1(dsaf_dev->dsaf_ver)) + reg_val_2 = 0x100 << dsaf_dev->reset_offset; + else + reg_val_2 = 0x40 << dsaf_dev->reset_offset;
reg_val_1 = 0x15540; reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40; reg_val_1 <<= dsaf_dev->reset_offset; reg_val_2 <<= dsaf_dev-
reset_offset;
if (!dereset) {
dsaf_write_sub(dsaf_dev,
DSAF_SUB_SC_GE_RESET_REQ1_REG,-- Andy Shevchenko [off-list ref] Intel Finland Oy