[PATCH 0/4] net: mvneta: support more than one clk

Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and "axi"
clk for the AXI bus logic.

This series tries to addess the "more than one clk" issue. Note: to
support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't
have mbus concept etc.

Jisheng Zhang (4):
  net: mvneta: sort the headers in alphabetic order
  net: mvneta: Try to get named core clock first
  net: mvneta: mmc: get optional axi clk
  net: mvneta: update clocks property and document additional
    clock-names

 .../bindings/net/marvell-armada-370-neta.txt       |  6 +++-
 drivers/net/ethernet/marvell/mvneta.c              | 36 ++++++++++++++--------
 2 files changed, 28 insertions(+), 14 deletions(-)

-- 
2.7.0.rc3

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Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and "axi"
clk for the AXI bus logic.

To support for more than one clock, we'll need to distinguish between
the clock by name. Change clock probing to first try to get "core"
clock before falling back to unnamed clock.

Signed-off-by: Jisheng Zhang <redacted>
---
 drivers/net/ethernet/marvell/mvneta.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 79e0c7d..aca0a73 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c

@@ -3605,7 +3605,9 @@ static int mvneta_probe(struct platform_device *pdev)
 
 	pp->indir[0] = rxq_def;
 
-	pp->clk = devm_clk_get(&pdev->dev, NULL);
+	pp->clk = devm_clk_get(&pdev->dev, "core");
+	if (IS_ERR(pp->clk))
+		pp->clk = devm_clk_get(&pdev->dev, NULL);
 	if (IS_ERR(pp->clk)) {
 		err = PTR_ERR(pp->clk);
 		goto err_put_phy_node;

-- 
2.7.0.rc3

Now that mvneta driver allows to have more than one clock defined,
update the clocks property and document the clock-names property.

Signed-off-by: Jisheng Zhang <redacted>
---
 Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index aeea50c..f85b93b 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt

@@ -6,12 +6,16 @@ Required properties:
 - interrupts: interrupt for the device
 - phy: See ethernet.txt file in the same directory.
 - phy-mode: See ethernet.txt file in the same directory
-- clocks: a pointer to the reference clock for this device.
+- clocks: Array of clocks required for this device; requires at least one
+  for CORE clock.
 
 Optional properties:
 - tx-csum-limit: maximum mtu supported by port that allow TX checksum.
   Value is presented in bytes. If not used, by default 1600B is set for
   "marvell,armada-370-neta" and 9800B for others.
+- clock-names: Array of names corresponding to clocks property; shall be
+  "core" for CORE clock and "axi" for optional AXI clock.
+
 
 Example:
 

-- 
2.7.0.rc3

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Sorting the headers in alphabetic order will help to reduce the conflict
when adding new headers in the future.

Signed-off-by: Jisheng Zhang <redacted>
---
 drivers/net/ethernet/marvell/mvneta.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index fabc8df..79e0c7d 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c

@@ -11,28 +11,28 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/kernel.h>
-#include <linux/netdevice.h>
+#include <linux/clk.h>
+#include <linux/cpu.h>
 #include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/skbuff.h>
-#include <linux/inetdevice.h>
+#include <linux/kernel.h>
 #include <linux/mbus.h>
 #include <linux/module.h>
-#include <linux/interrupt.h>
+#include <linux/netdevice.h>
 #include <linux/if_vlan.h>
-#include <net/ip.h>
-#include <net/ipv6.h>
+#include <linux/inetdevice.h>
+#include <linux/interrupt.h>
 #include <linux/io.h>
-#include <net/tso.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_mdio.h>
 #include <linux/of_net.h>
-#include <linux/of_address.h>
 #include <linux/phy.h>
-#include <linux/clk.h>
-#include <linux/cpu.h>
+#include <linux/platform_device.h>
+#include <linux/skbuff.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <net/tso.h>
 
 /* Registers */
 #define MVNETA_RXQ_CONFIG_REG(q)                (0x1400 + ((q) << 2))

-- 
2.7.0.rc3

Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and
"axi" clk for the AXI bus logic. Obviously this "axi" clk also need to
be enabled. This patch adds this optional "axi" clk support.

Signed-off-by: Jisheng Zhang <redacted>
---
 drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index aca0a73..6bb709a 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c

@@ -373,6 +373,8 @@ struct mvneta_port {
 
 	/* Core clock */
 	struct clk *clk;
+	/* AXI clock */
+	struct clk *clk_axi;
 	u8 mcast_count[256];
 	u16 tx_ring_size;
 	u16 rx_ring_size;

@@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev)
 
 	clk_prepare_enable(pp->clk);
 
+	pp->clk_axi = devm_clk_get(&pdev->dev, "axi");
+	if (!IS_ERR(pp->clk_axi))
+		clk_prepare_enable(pp->clk_axi);
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	pp->base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(pp->base)) {

@@ -3727,6 +3733,7 @@ err_free_ports:
 	free_percpu(pp->ports);
 err_clk:
 	clk_disable_unprepare(pp->clk);
+	clk_disable_unprepare(pp->clk_axi);
 err_put_phy_node:
 	of_node_put(phy_node);
 err_free_irq:

@@ -3744,6 +3751,7 @@ static int mvneta_remove(struct platform_device *pdev)
 
 	unregister_netdev(dev);
 	clk_disable_unprepare(pp->clk);
+	clk_disable_unprepare(pp->clk_axi);
 	free_percpu(pp->ports);
 	free_percpu(pp->stats);
 	irq_dispose_mapping(dev->irq);

-- 
2.7.0.rc3

Dear Jisheng Zhang,

On Wed, 20 Jan 2016 16:06:20 +0800, Jisheng Zhang wrote:

Sorting the headers in alphabetic order will help to reduce the conflict
when adding new headers in the future.

Signed-off-by: Jisheng Zhang <redacted>
---
 drivers/net/ethernet/marvell/mvneta.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

Acked-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

Thanks,

Thomas
-- 
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Dear Jisheng Zhang,

On Wed, 20 Jan 2016 16:06:21 +0800, Jisheng Zhang wrote:

Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and "axi"
clk for the AXI bus logic.

To support for more than one clock, we'll need to distinguish between
the clock by name. Change clock probing to first try to get "core"
clock before falling back to unnamed clock.

Signed-off-by: Jisheng Zhang <redacted>
---
 drivers/net/ethernet/marvell/mvneta.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Acked-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

Thanks,

Thomas
-- 
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Dear Jisheng Zhang,

On Wed, 20 Jan 2016 16:06:22 +0800, Jisheng Zhang wrote:

Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and
"axi" clk for the AXI bus logic. Obviously this "axi" clk also need to
be enabled. This patch adds this optional "axi" clk support.

Signed-off-by: Jisheng Zhang <redacted>

Typo in the title, you have "mmc: ", while this patch is not related to
MMC, unless I'm missing something and MMC means something else in this
context.

For the error paths and cleanup steps, I very much prefer when things
are done in the opposite order of the allocation/creation steps. So can
you clk_disable_unprepare() the AXI clock before the core clock ?

Ditto.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

On Wed, 20 Jan 2016 09:51:32 +0100 Thomas Petazzoni wrote:

Dear Jisheng Zhang,

On Wed, 20 Jan 2016 16:06:22 +0800, Jisheng Zhang wrote:

quoted

Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and
"axi" clk for the AXI bus logic. Obviously this "axi" clk also need to
be enabled. This patch adds this optional "axi" clk support.

Signed-off-by: Jisheng Zhang <redacted>  

Typo in the title, you have "mmc: ", while this patch is not related to
MMC, unless I'm missing something and MMC means something else in this
context.

oops, thanks for pointing out this.

quoted

 	clk_prepare_enable(pp->clk);
 
+	pp->clk_axi = devm_clk_get(&pdev->dev, "axi");
+	if (!IS_ERR(pp->clk_axi))
+		clk_prepare_enable(pp->clk_axi);
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	pp->base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(pp->base)) {

@@ -3727,6 +3733,7 @@ err_free_ports:
 	free_percpu(pp->ports);
 err_clk:
 	clk_disable_unprepare(pp->clk);
+	clk_disable_unprepare(pp->clk_axi);  

For the error paths and cleanup steps, I very much prefer when things
are done in the opposite order of the allocation/creation steps. So can
you clk_disable_unprepare() the AXI clock before the core clock ?

Both are fine. But I agree with your prefer. Will cook a v2 soon

Thanks for reviewing.

quoted

 err_put_phy_node:
 	of_node_put(phy_node);
 err_free_irq:

@@ -3744,6 +3751,7 @@ static int mvneta_remove(struct platform_device *pdev)
 
 	unregister_netdev(dev);
 	clk_disable_unprepare(pp->clk);
+	clk_disable_unprepare(pp->clk_axi);  

Ditto.

Thanks!

Thomas

Dear Jisheng Zhang,

On Wed, 20 Jan 2016 16:06:23 +0800, Jisheng Zhang wrote:

Rather than "Array", I would say "list", so what about:

 - clocks: List of clocks for this device. At least one clock is
   mandatory for the core clock. If several clocks are given, then the
   clock-names property must be used to identify them.

 Optional properties:
 - tx-csum-limit: maximum mtu supported by port that allow TX checksum.
   Value is presented in bytes. If not used, by default 1600B is set for
   "marvell,armada-370-neta" and 9800B for others.
+- clock-names: Array of names corresponding to clocks property; shall be
+  "core" for CORE clock and "axi" for optional AXI clock.

Array -> List.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

On January 20, 2016 9:15:22 AM Jisheng Zhang [off-list ref] wrote:

Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and
"axi" clk for the AXI bus logic. Obviously this "axi" clk also need to
be enabled. This patch adds this optional "axi" clk support.

Jisheng,

although I do not expect mvneta to appear on a non-AXI bus
anytime soon, how about naming the clock "bus" instead?

If you know the clock is only required for bus master DMA but
not for register access, "dma" would be an even better name.

Sebastian

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On Wed, 20 Jan 2016 10:31:18 +0100 Sebastian Hesselbarth  wrote:

On January 20, 2016 9:15:22 AM Jisheng Zhang wrote:

quoted

Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and
"axi" clk for the AXI bus logic. Obviously this "axi" clk also need to
be enabled. This patch adds this optional "axi" clk support.  

Jisheng,

although I do not expect mvneta to appear on a non-AXI bus
anytime soon, how about naming the clock "bus" instead?

Good question. IIRC, this IP expects AXI bus, but I'll check with HW people.

Thanks a lot,
Jisheng

If you know the clock is only required for bus master DMA but
not for register access, "dma" would be an even better name.

Sebastian

quoted

Signed-off-by: Jisheng Zhang <redacted>
---
 drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 

b/drivers/net/ethernet/marvell/mvneta.c
index aca0a73..6bb709a 100644

--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c

@@ -373,6 +373,8 @@ struct mvneta_port {

 	/* Core clock */
 	struct clk *clk;
+	/* AXI clock */
+	struct clk *clk_axi;
 	u8 mcast_count[256];
 	u16 tx_ring_size;
 	u16 rx_ring_size;

@@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev)

 	clk_prepare_enable(pp->clk);

+	pp->clk_axi = devm_clk_get(&pdev->dev, "axi");
+	if (!IS_ERR(pp->clk_axi))
+		clk_prepare_enable(pp->clk_axi);
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	pp->base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(pp->base)) {

@@ -3727,6 +3733,7 @@ err_free_ports:
 	free_percpu(pp->ports);
 err_clk:
 	clk_disable_unprepare(pp->clk);
+	clk_disable_unprepare(pp->clk_axi);
 err_put_phy_node:
 	of_node_put(phy_node);
 err_free_irq:

@@ -3744,6 +3751,7 @@ static int mvneta_remove(struct platform_device *pdev)

 	unregister_netdev(dev);
 	clk_disable_unprepare(pp->clk);
+	clk_disable_unprepare(pp->clk_axi);
 	free_percpu(pp->ports);
 	free_percpu(pp->stats);
 	irq_dispose_mapping(dev->irq);
--

2.7.0.rc3
 

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On 01/20/2016 10:42 AM, Jisheng Zhang wrote:

On Wed, 20 Jan 2016 10:31:18 +0100 Sebastian Hesselbarth  wrote:

quoted

On January 20, 2016 9:15:22 AM Jisheng Zhang wrote:

quoted

Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and
"axi" clk for the AXI bus logic. Obviously this "axi" clk also need to
be enabled. This patch adds this optional "axi" clk support.

Jisheng,

although I do not expect mvneta to appear on a non-AXI bus
anytime soon, how about naming the clock "bus" instead?

Good question. IIRC, this IP expects AXI bus, but I'll check with HW people.

Actually, I am quite sure the current IP requires AXI. But my comment
was more about to make the binding a little bit more flexible to
_future_ variants/SoCs we may stumble upon.

Naming the clock "bus" or "dma" will work for the current _and_ future
IPs, while "axi" may not.

Sebastian

quoted

If you know the clock is only required for bus master DMA but
not for register access, "dma" would be an even better name.

Sebastian

quoted

Signed-off-by: Jisheng Zhang <redacted>
---
  drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++
  1 file changed, 8 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mvneta.c

b/drivers/net/ethernet/marvell/mvneta.c
index aca0a73..6bb709a 100644

--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c

@@ -373,6 +373,8 @@ struct mvneta_port {

  	/* Core clock */
  	struct clk *clk;
+	/* AXI clock */
+	struct clk *clk_axi;
  	u8 mcast_count[256];
  	u16 tx_ring_size;
  	u16 rx_ring_size;

@@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev)

  	clk_prepare_enable(pp->clk);

+	pp->clk_axi = devm_clk_get(&pdev->dev, "axi");
+	if (!IS_ERR(pp->clk_axi))
+		clk_prepare_enable(pp->clk_axi);
+
  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  	pp->base = devm_ioremap_resource(&pdev->dev, res);
  	if (IS_ERR(pp->base)) {

@@ -3727,6 +3733,7 @@ err_free_ports:
  	free_percpu(pp->ports);
  err_clk:
  	clk_disable_unprepare(pp->clk);
+	clk_disable_unprepare(pp->clk_axi);
  err_put_phy_node:
  	of_node_put(phy_node);
  err_free_irq:

@@ -3744,6 +3751,7 @@ static int mvneta_remove(struct platform_device *pdev)

  	unregister_netdev(dev);
  	clk_disable_unprepare(pp->clk);
+	clk_disable_unprepare(pp->clk_axi);
  	free_percpu(pp->ports);
  	free_percpu(pp->stats);
  	irq_dispose_mapping(dev->irq);
--

2.7.0.rc3

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Dear Sebastian,

On Wed, 20 Jan 2016 12:03:03 +0100 Sebastian Hesselbarth wrote:

On 01/20/2016 10:42 AM, Jisheng Zhang wrote:

quoted

On Wed, 20 Jan 2016 10:31:18 +0100 Sebastian Hesselbarth  wrote:
 

quoted

On January 20, 2016 9:15:22 AM Jisheng Zhang wrote:
 

quoted

Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and
"axi" clk for the AXI bus logic. Obviously this "axi" clk also need to
be enabled. This patch adds this optional "axi" clk support.  

Jisheng,

although I do not expect mvneta to appear on a non-AXI bus
anytime soon, how about naming the clock "bus" instead?  

Good question. IIRC, this IP expects AXI bus, but I'll check with HW people.  

Actually, I am quite sure the current IP requires AXI. But my comment
was more about to make the binding a little bit more flexible to
_future_ variants/SoCs we may stumble upon.

Got your points. PS: the clk is for AXI bus logic, so "bus" makes sense.

Naming the clock "bus" or "dma" will work for the current _and_ future
IPs, while "axi" may not.

Indeed, will cook a v3

Thanks a lot for review,
Jisheng

Sebastian

quoted

quoted

If you know the clock is only required for bus master DMA but
not for register access, "dma" would be an even better name.

Sebastian

 

quoted

Signed-off-by: Jisheng Zhang <redacted>
---
  drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++
  1 file changed, 8 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mvneta.c

b/drivers/net/ethernet/marvell/mvneta.c
index aca0a73..6bb709a 100644

--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c

@@ -373,6 +373,8 @@ struct mvneta_port {

  	/* Core clock */
  	struct clk *clk;
+	/* AXI clock */
+	struct clk *clk_axi;
  	u8 mcast_count[256];
  	u16 tx_ring_size;
  	u16 rx_ring_size;

@@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev)

  	clk_prepare_enable(pp->clk);

+	pp->clk_axi = devm_clk_get(&pdev->dev, "axi");
+	if (!IS_ERR(pp->clk_axi))
+		clk_prepare_enable(pp->clk_axi);
+
  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  	pp->base = devm_ioremap_resource(&pdev->dev, res);
  	if (IS_ERR(pp->base)) {

@@ -3727,6 +3733,7 @@ err_free_ports:
  	free_percpu(pp->ports);
  err_clk:
  	clk_disable_unprepare(pp->clk);
+	clk_disable_unprepare(pp->clk_axi);
  err_put_phy_node:
  	of_node_put(phy_node);
  err_free_irq:

@@ -3744,6 +3751,7 @@ static int mvneta_remove(struct platform_device *pdev)

  	unregister_netdev(dev);
  	clk_disable_unprepare(pp->clk);
+	clk_disable_unprepare(pp->clk_axi);
  	free_percpu(pp->ports);
  	free_percpu(pp->stats);
  	irq_dispose_mapping(dev->irq);
--

2.7.0.rc3
 

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