Hi Don,

On Wed, Mar 18, 2015 at 07:07:34PM -0700, Don Fry wrote:

One little change to the comment is needed.  See below

Don

On Wed, 2015-03-18 at 20:10 +0000, Markos Chandras wrote:

quoted

+	if (sram) {
+		/*
+		 * The SRAM is being configured in two steps. First we
+		 * set the SRAM size in the BCR25:SRAM_SIZE bits. According
+		 * to the datasheet, each bit corresponds to a 512-byte
+		 * page so we can have at most 24 pages. The SRAM_SIZE
+		 * corresponds holds the value of the upper 8 bits of
+		 * the 16-bit SRAM size. The low 8-bits start at 0x00
+		 * and end at 0xff. So the address range is from 0x0000
+		 * up to 0x17ff. Therefore, the SRAM_SIZE is set to 0x17.
+		 * The next step is to set the BCR24:SRAM_BND midway through
+		 * so the Tx and Rx buffers can share the SRAM equally.
+		 */

The comment specifies BCR24 but the code is changing BCR26 which matches
the documentation.  Please correct the comment to avoid confusion.

Ah good catch. I will fix it and send a v2.

-- 
markos