Re: [PATCH] net/cadence/macb: clear interrupts simply and correctly

On 06/17/2014 12:50 PM, Sören Brinkmann wrote:

On Tue, 2014-06-17 at 11:38AM +0900, Jongsung Kim wrote:

quoted

On 06/16/2014 11:56 PM, Sören Brinkmann wrote:

quoted

On Mon, 2014-06-16 at 02:00PM +0900, Jongsung Kim wrote:

quoted

On 06/13/2014 12:44 AM, Sören Brinkmann wrote:

quoted

This is now clearing all IRQ flags which is probably not what we want
here. This is handling RX only. We still want the non-RX interrupts to go to
the actual interrupt service routing.

The ISR(Interrupt Status Register) is read only in the interrupt service
routine, macb_interrupt. But is partially cleared here and there. Further
handler-functions decide jobs to be done by reading/checking other status
registers. (e.g., TSR, RSR) So, clearing the ISR after reading looks not
a bad idea.

But you are clearing _all_ interrupt flags in the RX NAPI handler.
Doesn't that mean we might miss certain events?

Please inspect my patch again. What I did in the macb_poll is removing
statements clearing the Rx-complete interrupt, not clearing all the
interrupts.

Why is clearing those bits removed? It's probably not a big hit, but it might
result in a pointless interrupt which could be avoided. But it should
probably clear all RX interrupts - MACB_RX_INT_FLAGS - instead of just RCOMP.
For clear-on-read implementations it shouldn't make a difference.

I agree. But I removed it because I think stepping the same procedure
regardless of the "gem_irq_clear_read" implementation is better than
implementation-specific optimization.

And in the if-condition in that new helper, I'd add '&& status' to
avoid writing back zeros.

Good point. I'll add it when I resend v2.

Jongsung